[llvm] r364534 - [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.

[Simon Tatham via llvm-commits]

Author: statham
Date: Thu Jun 27 05:41:12 2019
New Revision: 364534

URL: http://llvm.org/viewvc/llvm-project?rev=364534&view=rev
Log:
[ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.

The code to generate register move instructions in and out of VPR and
FPSCR_NZCV had assertions checking that the other register involved
was a GPR _pair_, instead of a single GPR as it should have been.

Reviewers: miyuki, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63865

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=364534&r1=364533&r2=364534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 27 05:41:12 2019
@@ -927,25 +927,25 @@ void ARMBaseInstrInfo::copyPhysReg(Machi
     copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
     return;
   } else if (DestReg == ARM::VPR) {
-    assert(ARM::GPRPairRegClass.contains(SrcReg));
+    assert(ARM::GPRRegClass.contains(SrcReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (SrcReg == ARM::VPR) {
-    assert(ARM::GPRPairRegClass.contains(DestReg));
+    assert(ARM::GPRRegClass.contains(DestReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (DestReg == ARM::FPSCR_NZCV) {
-    assert(ARM::GPRPairRegClass.contains(SrcReg));
+    assert(ARM::GPRRegClass.contains(SrcReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
     return;
   } else if (SrcReg == ARM::FPSCR_NZCV) {
-    assert(ARM::GPRPairRegClass.contains(DestReg));
+    assert(ARM::GPRRegClass.contains(DestReg));
     BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));