[PATCH] D63862: [ARM] Tighten restrictions on use of SP in v8.1-M CSEL.

Simon Tatham via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 27 02:49:29 PDT 2019


simon_tatham created this revision.
simon_tatham added reviewers: DavidSpickett, ostannard.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

In the `CSEL Rd,Rm,Rn` instruction family (also including CSINC, CSINV
and CSNEG), the architecture lists it as CONSTRAINED UNPREDICTABLE
(i.e. SoftFail) to use SP in the Rd or Rm slot, but outright illegal
to use it in the Rn slot, not least because some encodings of that
form are used by MVE instructions such as UQRSHLL.

MC was treating all three slots the same, as SoftFail. So the only
reason UQRSHLL was disassembled correctly at all was because the MVE
decode table is separate from the Thumb2 one and takes priority; if
you turned off MVE, then encodings such as `[0x5f,0xea,0x0d,0x83]`
would disassemble as spurious CSELs.

Fixed by inventing another version of the `GPRwithZR` register class,
which disallows SP completely instead of just SoftFailing it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D63862

Files:
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/test/MC/Disassembler/ARM/mve-scalar-shift.txt
  llvm/test/MC/Disassembler/ARM/thumbv8.1m.s

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