[PATCH] D63849: AMDGPU: Make s34 the FP register

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, scott.linder, t-tye.
Herald added subscribers: arphaman, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.

Make the FP register callee saved.

      

This is tricky because now the FP needs to be spilled in the prolog
relative to the incoming SP register, rather than the frame register
used throughout the rest of the function. I don't like how this
bypassess the standard mechanism for CSR spills just to get the
correct insert point. I may look for a better solution, since all CSR
VGPRs may also need to have all lanes activated. Another option might
be to make getFrameIndexReference change the base register if the
frame index is a CSR, and then try to figure out the right insertion
point in emitProlog.

      

If there is a free VGPR lane available for SGPR spilling, try to use
it for the FP. If that would require intrtoducing a new VGPR spill,
try to use a free call clobbered SGPR. Only fallback to introducing a
new VGPR spill as a last resort.

      

This also doesn't attempt to handle SGPR spilling with scalar stores.


https://reviews.llvm.org/D63849

Files:
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIFrameLowering.h
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  test/CodeGen/AMDGPU/atomicrmw-nand.ll
  test/CodeGen/AMDGPU/byval-frame-setup.ll
  test/CodeGen/AMDGPU/call-graph-register-usage.ll
  test/CodeGen/AMDGPU/call-preserved-registers.ll
  test/CodeGen/AMDGPU/call-waitcnt.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/frame-index-elimination.ll
  test/CodeGen/AMDGPU/function-returns.ll
  test/CodeGen/AMDGPU/ipra.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
  test/CodeGen/AMDGPU/mad_64_32.ll
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/shift-i128.ll
  test/CodeGen/AMDGPU/sibling-call.ll
  test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  test/CodeGen/AMDGPU/spill-offset-calculation.ll
  test/CodeGen/AMDGPU/stack-realign.ll
  test/CodeGen/AMDGPU/wave32.ll

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