[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

[Piotr Sobczak via Phabricator via llvm-commits]

piotr added a comment.

In D63709#1557689 <https://reviews.llvm.org/D63709#1557689>, @arsenm wrote:

> I think things are going from from this heuristic:
>
>   // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
>   // it unless the defined value is already used in the BB of the new use.
>   bool HasPHI = false;
>   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
>     HasPHI |= UseMI.isPHI();
>     if (UseMI.getParent() == MI->getParent())
>       return true;
>   }
>   
>   
>
> The second phi use is in a flow block with only the phi, so the use is in the fall through successor. Maybe it could be relaxed to look through trivial successors, at least for blocks with only phis?


Nice tracking down. I will abandon this review, and submit another one where I will extend the MachineCSE pass as you suggested.


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