[PATCH] D63624: [PowerPC] Exploit single instruction load-and-splat for word and doubleword

[Amy Kwan via Phabricator via llvm-commits]

amyk added a comment.

Thanks @jsji for letting me know, and thanks @nemanjai for the handling of the load and splats!

I think this mostly looks good to me. I'm curious though, we also have `test/CodeGen/PowerPC/load-v4i8-improved.ll` that has a load->shift/permute->splat case. Could this patch be extended to cover this?

That test case is as follows:

  define <16 x i8> @test(i32* %s, i32* %t) {
  ; CHECK-LE-LABEL: test:
  ; CHECK-LE:       # %bb.0: # %entry
  ; CHECK-LE-NEXT:    lfiwzx f0, 0, r3
  ; CHECK-LE-NEXT:    xxpermdi vs0, f0, f0, 2
  ; CHECK-LE-NEXT:    xxspltw v2, vs0, 3
  ; CHECK-LE-NEXT:    blr
  
  ; CHECK-LABEL: test:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    lfiwzx f0, 0, r3
  ; CHECK-NEXT:    xxsldwi vs0, f0, f0, 1
  ; CHECK-NEXT:    xxspltw v2, vs0, 0
  ; CHECK-NEXT:    blr
  entry:
    %0 = bitcast i32* %s to <4 x i8>*
    %1 = load <4 x i8>, <4 x i8>* %0, align 4
    %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
    ret <16 x i8> %2
  }


Repository:
  rL LLVM

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https://reviews.llvm.org/D63624