[llvm] r364425 - AMDGPU: Check MRI for callee saved regs instead of TRI

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Jun 26 06:39:29 2019
New Revision: 364425

URL: http://llvm.org/viewvc/llvm-project?rev=364425&view=rev
Log:
AMDGPU: Check MRI for callee saved regs instead of TRI

This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.

Modified:
    llvm/trunk/lib/Target/AMDGPU/GCNNSAReassign.cpp
    llvm/trunk/lib/Target/AMDGPU/GCNRegBankReassign.cpp
    llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
    llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/GCNNSAReassign.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNNSAReassign.cpp?rev=364425&r1=364424&r2=364425&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNNSAReassign.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNNSAReassign.cpp Wed Jun 26 06:39:29 2019
@@ -234,7 +234,7 @@ bool GCNNSAReassign::runOnMachineFunctio
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
   MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);
-  CSRegs = TRI->getCalleeSavedRegs(&MF);
+  CSRegs = MRI->getCalleeSavedRegs();
 
   using Candidate = std::pair<const MachineInstr*, bool>;
   SmallVector<Candidate, 32> Candidates;

Modified: llvm/trunk/lib/Target/AMDGPU/GCNRegBankReassign.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNRegBankReassign.cpp?rev=364425&r1=364424&r2=364425&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNRegBankReassign.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNRegBankReassign.cpp Wed Jun 26 06:39:29 2019
@@ -740,7 +740,7 @@ bool GCNRegBankReassign::runOnMachineFun
   MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs);
   MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs);
 
-  CSRegs = TRI->getCalleeSavedRegs(&MF);
+  CSRegs = MRI->getCalleeSavedRegs();
 
   RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() +
                   TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1);

Modified: llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp?rev=364425&r1=364424&r2=364425&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp Wed Jun 26 06:39:29 2019
@@ -527,15 +527,13 @@ static unsigned findScratchNonCalleeSave
                                                  LivePhysRegs &LiveRegs,
                                                  const TargetRegisterClass &RC) {
   const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
-  const SIRegisterInfo &TRI = *Subtarget.getRegisterInfo();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
 
   // Mark callee saved registers as used so we will not choose them.
-  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
+  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
   for (unsigned i = 0; CSRegs[i]; ++i)
     LiveRegs.addReg(CSRegs[i]);
 
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-
   for (unsigned Reg : RC) {
     if (LiveRegs.available(MRI, Reg))
       return Reg;

Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=364425&r1=364424&r2=364425&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Wed Jun 26 06:39:29 2019
@@ -250,7 +250,7 @@ bool SIMachineFunctionInfo::allocateSGPR
 
   int NumLanes = Size / 4;
 
-  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
+  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
 
   // Make sure to handle the case where a wide SGPR spill may span between two
   // VGPRs.