[PATCH] D62685: [RISCV] Add pseudo instruction for calls with explicit register

[Lewis Revill via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL364403: [RISCV] Add pseudo instruction for calls with explicit register (authored by lewis-revill, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D62685?vs=205616&id=206622#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62685/new/

https://reviews.llvm.org/D62685

Files:
  llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/trunk/test/MC/RISCV/function-call-invalid.s
  llvm/trunk/test/MC/RISCV/function-call.s

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