[llvm] r364393 - [NFC][InstCombine] Add shift amount reassociation tests (PR42391)
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 01:17:05 PDT 2019
Author: lebedevri
Date: Wed Jun 26 01:17:05 2019
New Revision: 364393
URL: http://llvm.org/viewvc/llvm-project?rev=364393&view=rev
Log:
[NFC][InstCombine] Add shift amount reassociation tests (PR42391)
https://bugs.llvm.org/show_bug.cgi?id=42391
https://rise4fun.com/Alive/9E2
Added:
llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation.ll
Added: llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation.ll?rev=364393&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation.ll Wed Jun 26 01:17:05 2019
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; Given pattern:
+; (x shiftopcode Q) shiftopcode K
+; we should rewrite it as
+; x shiftopcode (Q+K) iff (Q+K) u< bitwidth(x)
+; This is valid for any shift, but they must be identical.
+
+; Basic scalar test
+
+define i32 @t0(i32 %x, i32 %y) {
+; CHECK-LABEL: @t0(
+; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -2
+; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = sub i32 32, %y
+ %t1 = lshr i32 %x, %t0
+ %t2 = add i32 %y, -2
+ %t3 = lshr i32 %t1, %t2
+ ret i32 %t3
+}
+
+define <2 x i32> @t1_vec_splat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t1_vec_splat(
+; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 32>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[Y]], <i32 -2, i32 -2>
+; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <2 x i32> [[T3]]
+;
+ %t0 = sub <2 x i32> <i32 32, i32 32>, %y
+ %t1 = lshr <2 x i32> %x, %t0
+ %t2 = add <2 x i32> %y, <i32 -2, i32 -2>
+ %t3 = lshr <2 x i32> %t1, %t2
+ ret <2 x i32> %t3
+}
+
+define <2 x i32> @t2_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t2_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 30>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[Y]], <i32 -2, i32 0>
+; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <2 x i32> [[T3]]
+;
+ %t0 = sub <2 x i32> <i32 32, i32 30>, %y
+ %t1 = lshr <2 x i32> %x, %t0
+ %t2 = add <2 x i32> %y, <i32 -2, i32 0>
+ %t3 = lshr <2 x i32> %t1, %t2
+ ret <2 x i32> %t3
+}
+
+; Basic vector tests
+
+define <3 x i32> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t3_vec_nonsplat_undef0(
+; CHECK-NEXT: [[T0:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[Y]], <i32 -2, i32 -2, i32 -2>
+; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %y
+ %t1 = lshr <3 x i32> %x, %t0
+ %t2 = add <3 x i32> %y, <i32 -2, i32 -2, i32 -2>
+ %t3 = lshr <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t4_vec_nonsplat_undef1(
+; CHECK-NEXT: [[T0:%.*]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[Y]], <i32 -2, i32 undef, i32 -2>
+; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = sub <3 x i32> <i32 32, i32 32, i32 32>, %y
+ %t1 = lshr <3 x i32> %x, %t0
+ %t2 = add <3 x i32> %y, <i32 -2, i32 undef, i32 -2>
+ %t3 = lshr <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @t5_vec_nonsplat_undef1(
+; CHECK-NEXT: [[T0:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[Y]], <i32 -2, i32 undef, i32 -2>
+; CHECK-NEXT: [[T3:%.*]] = lshr <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %y
+ %t1 = lshr <3 x i32> %x, %t0
+ %t2 = add <3 x i32> %y, <i32 -2, i32 undef, i32 -2>
+ %t3 = lshr <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+; Some other shift opcodes
+define i32 @t6_shl(i32 %x, i32 %y) {
+; CHECK-LABEL: @t6_shl(
+; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -2
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = sub i32 32, %y
+ %t1 = shl i32 %x, %t0
+ %t2 = add i32 %y, -2
+ %t3 = shl i32 %t1, %t2
+ ret i32 %t3
+}
+define i32 @t7_ashr(i32 %x, i32 %y) {
+; CHECK-LABEL: @t7_ashr(
+; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], -2
+; CHECK-NEXT: [[T3:%.*]] = ashr i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = sub i32 32, %y
+ %t1 = ashr i32 %x, %t0
+ %t2 = add i32 %y, -2
+ %t3 = ashr i32 %t1, %t2
+ ret i32 %t3
+}
+
+; No one-use tests since we will only produce a single instruction here.
+
+; Negative tests
+
+; Can't fold, total shift would be 32
+define i32 @n8(i32 %x, i32 %y) {
+; CHECK-LABEL: @n8(
+; CHECK-NEXT: [[T0:%.*]] = sub i32 30, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[Y]], 2
+; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = sub i32 30, %y
+ %t1 = lshr i32 %x, %t0
+ %t2 = add i32 %y, 2
+ %t3 = lshr i32 %t1, %t2
+ ret i32 %t3
+}
+; Can't fold, for second channel the shift would 32
+define <2 x i32> @t9_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t9_vec(
+; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 30>, [[Y:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[Y]], <i32 -2, i32 2>
+; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <2 x i32> [[T3]]
+;
+ %t0 = sub <2 x i32> <i32 32, i32 30>, %y
+ %t1 = lshr <2 x i32> %x, %t0
+ %t2 = add <2 x i32> %y, <i32 -2, i32 2>
+ %t3 = lshr <2 x i32> %t1, %t2
+ ret <2 x i32> %t3
+}
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