[PATCH] D55251: [X86] Enable -x86-experimental-vector-widening-legalization by default.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 01:06:06 PDT 2019
craig.topper updated this revision to Diff 206607.
craig.topper added a comment.
Rebase
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D55251/new/
https://reviews.llvm.org/D55251
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll
llvm/test/Analysis/CostModel/X86/arith.ll
llvm/test/Analysis/CostModel/X86/cast.ll
llvm/test/Analysis/CostModel/X86/fptosi.ll
llvm/test/Analysis/CostModel/X86/fptoui.ll
llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
llvm/test/Analysis/CostModel/X86/reduce-add.ll
llvm/test/Analysis/CostModel/X86/reduce-and.ll
llvm/test/Analysis/CostModel/X86/reduce-mul.ll
llvm/test/Analysis/CostModel/X86/reduce-or.ll
llvm/test/Analysis/CostModel/X86/reduce-smax.ll
llvm/test/Analysis/CostModel/X86/reduce-smin.ll
llvm/test/Analysis/CostModel/X86/reduce-umax.ll
llvm/test/Analysis/CostModel/X86/reduce-umin.ll
llvm/test/Analysis/CostModel/X86/reduce-xor.ll
llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
llvm/test/Analysis/CostModel/X86/sitofp.ll
llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll
llvm/test/Analysis/CostModel/X86/testshiftashr.ll
llvm/test/Analysis/CostModel/X86/testshiftlshr.ll
llvm/test/Analysis/CostModel/X86/testshiftshl.ll
llvm/test/Analysis/CostModel/X86/uitofp.ll
llvm/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
llvm/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
llvm/test/CodeGen/X86/2011-12-28-vselecti8.ll
llvm/test/CodeGen/X86/2011-12-8-bitcastintprom.ll
llvm/test/CodeGen/X86/2012-01-18-vbitcast.ll
llvm/test/CodeGen/X86/2012-03-15-build_vector_wl.ll
llvm/test/CodeGen/X86/2012-07-10-extload64.ll
llvm/test/CodeGen/X86/3dnow-intrinsics.ll
llvm/test/CodeGen/X86/4char-promote.ll
llvm/test/CodeGen/X86/and-load-fold.ll
llvm/test/CodeGen/X86/atomic-unordered.ll
llvm/test/CodeGen/X86/avg.ll
llvm/test/CodeGen/X86/avx-cvt-2.ll
llvm/test/CodeGen/X86/avx-fp2int.ll
llvm/test/CodeGen/X86/avx2-conversions.ll
llvm/test/CodeGen/X86/avx2-masked-gather.ll
llvm/test/CodeGen/X86/avx2-vbroadcast.ll
llvm/test/CodeGen/X86/avx512-any_extend_load.ll
llvm/test/CodeGen/X86/avx512-cvt.ll
llvm/test/CodeGen/X86/avx512-ext.ll
llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
llvm/test/CodeGen/X86/avx512-mask-op.ll
llvm/test/CodeGen/X86/avx512-trunc.ll
llvm/test/CodeGen/X86/avx512-vec-cmp.ll
llvm/test/CodeGen/X86/avx512-vec3-crash.ll
llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll
llvm/test/CodeGen/X86/bitcast-setcc-128.ll
llvm/test/CodeGen/X86/bitcast-vector-bool.ll
llvm/test/CodeGen/X86/bitreverse.ll
llvm/test/CodeGen/X86/bswap-vector.ll
llvm/test/CodeGen/X86/buildvec-insertvec.ll
llvm/test/CodeGen/X86/combine-64bit-vec-binop.ll
llvm/test/CodeGen/X86/combine-or.ll
llvm/test/CodeGen/X86/cvtv2f32.ll
llvm/test/CodeGen/X86/extract-concat.ll
llvm/test/CodeGen/X86/extract-insert.ll
llvm/test/CodeGen/X86/f16c-intrinsics.ll
llvm/test/CodeGen/X86/fold-vector-sext-zext.ll
llvm/test/CodeGen/X86/insertelement-shuffle.ll
llvm/test/CodeGen/X86/known-bits-vector.ll
llvm/test/CodeGen/X86/known-bits.ll
llvm/test/CodeGen/X86/known-signbits-vector.ll
llvm/test/CodeGen/X86/lower-bitcast.ll
llvm/test/CodeGen/X86/madd.ll
llvm/test/CodeGen/X86/masked_compressstore.ll
llvm/test/CodeGen/X86/masked_expandload.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
llvm/test/CodeGen/X86/masked_load.ll
llvm/test/CodeGen/X86/masked_store.ll
llvm/test/CodeGen/X86/masked_store_trunc.ll
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
llvm/test/CodeGen/X86/mmx-arg-passing-x86-64.ll
llvm/test/CodeGen/X86/mmx-arith.ll
llvm/test/CodeGen/X86/mmx-cvt.ll
llvm/test/CodeGen/X86/mulvi32.ll
llvm/test/CodeGen/X86/oddshuffles.ll
llvm/test/CodeGen/X86/oddsubvector.ll
llvm/test/CodeGen/X86/paddus.ll
llvm/test/CodeGen/X86/pmaddubsw.ll
llvm/test/CodeGen/X86/pmulh.ll
llvm/test/CodeGen/X86/pointer-vector.ll
llvm/test/CodeGen/X86/pr14161.ll
llvm/test/CodeGen/X86/pr35918.ll
llvm/test/CodeGen/X86/pr40994.ll
llvm/test/CodeGen/X86/promote-vec3.ll
llvm/test/CodeGen/X86/promote.ll
llvm/test/CodeGen/X86/psubus.ll
llvm/test/CodeGen/X86/ret-mmx.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/sadd_sat_vec.ll
llvm/test/CodeGen/X86/scalar_widen_div.ll
llvm/test/CodeGen/X86/select.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
llvm/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
llvm/test/CodeGen/X86/slow-pmulld.ll
llvm/test/CodeGen/X86/sse2-intrinsics-canonical.ll
llvm/test/CodeGen/X86/sse2-vector-shifts.ll
llvm/test/CodeGen/X86/ssub_sat_vec.ll
llvm/test/CodeGen/X86/test-shrink-bug.ll
llvm/test/CodeGen/X86/trunc-ext-ld-st.ll
llvm/test/CodeGen/X86/trunc-subvector.ll
llvm/test/CodeGen/X86/uadd_sat_vec.ll
llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
llvm/test/CodeGen/X86/usub_sat_vec.ll
llvm/test/CodeGen/X86/vec_cast2.ll
llvm/test/CodeGen/X86/vec_cast3.ll
llvm/test/CodeGen/X86/vec_ctbits.ll
llvm/test/CodeGen/X86/vec_extract-mmx.ll
llvm/test/CodeGen/X86/vec_fp_to_int.ll
llvm/test/CodeGen/X86/vec_insert-5.ll
llvm/test/CodeGen/X86/vec_insert-7.ll
llvm/test/CodeGen/X86/vec_insert-mmx.ll
llvm/test/CodeGen/X86/vec_int_to_fp.ll
llvm/test/CodeGen/X86/vec_saddo.ll
llvm/test/CodeGen/X86/vec_smulo.ll
llvm/test/CodeGen/X86/vec_ssubo.ll
llvm/test/CodeGen/X86/vec_uaddo.ll
llvm/test/CodeGen/X86/vec_umulo.ll
llvm/test/CodeGen/X86/vec_usubo.ll
llvm/test/CodeGen/X86/vector-blend.ll
llvm/test/CodeGen/X86/vector-ext-logic.ll
llvm/test/CodeGen/X86/vector-gep.ll
llvm/test/CodeGen/X86/vector-half-conversions.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
llvm/test/CodeGen/X86/vector-narrow-binop.ll
llvm/test/CodeGen/X86/vector-reduce-add.ll
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
llvm/test/CodeGen/X86/vector-reduce-and.ll
llvm/test/CodeGen/X86/vector-reduce-mul.ll
llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
llvm/test/CodeGen/X86/vector-reduce-or.ll
llvm/test/CodeGen/X86/vector-reduce-smax.ll
llvm/test/CodeGen/X86/vector-reduce-smin.ll
llvm/test/CodeGen/X86/vector-reduce-umax.ll
llvm/test/CodeGen/X86/vector-reduce-umin.ll
llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
llvm/test/CodeGen/X86/vector-reduce-xor.ll
llvm/test/CodeGen/X86/vector-sext.ll
llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-combining.ll
llvm/test/CodeGen/X86/vector-trunc-packus.ll
llvm/test/CodeGen/X86/vector-trunc-ssat.ll
llvm/test/CodeGen/X86/vector-trunc-usat.ll
llvm/test/CodeGen/X86/vector-trunc.ll
llvm/test/CodeGen/X86/vector-truncate-combine.ll
llvm/test/CodeGen/X86/vector-zext.ll
llvm/test/CodeGen/X86/vsel-cmp-load.ll
llvm/test/CodeGen/X86/vselect-avx.ll
llvm/test/CodeGen/X86/vselect.ll
llvm/test/CodeGen/X86/vshift-4.ll
llvm/test/CodeGen/X86/widen_arith-1.ll
llvm/test/CodeGen/X86/widen_arith-2.ll
llvm/test/CodeGen/X86/widen_arith-3.ll
llvm/test/CodeGen/X86/widen_bitops-0.ll
llvm/test/CodeGen/X86/widen_cast-1.ll
llvm/test/CodeGen/X86/widen_cast-2.ll
llvm/test/CodeGen/X86/widen_cast-3.ll
llvm/test/CodeGen/X86/widen_cast-4.ll
llvm/test/CodeGen/X86/widen_cast-5.ll
llvm/test/CodeGen/X86/widen_cast-6.ll
llvm/test/CodeGen/X86/widen_compare-1.ll
llvm/test/CodeGen/X86/widen_conv-1.ll
llvm/test/CodeGen/X86/widen_conv-2.ll
llvm/test/CodeGen/X86/widen_conv-3.ll
llvm/test/CodeGen/X86/widen_conv-4.ll
llvm/test/CodeGen/X86/widen_load-2.ll
llvm/test/CodeGen/X86/widen_shuffle-1.ll
llvm/test/CodeGen/X86/x86-interleaved-access.ll
llvm/test/CodeGen/X86/x86-shifts.ll
llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
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