[PATCH] D63806: [PowerPC][Peephole] Combine extsw and sldi after instruction selection

[Kai Luo via Phabricator via llvm-commits]

lkail created this revision.
lkail added reviewers: steven.zhang, jsji, nemanjai, hfinkel.
Herald added subscribers: llvm-commits, kbarton, hiraditya.
Herald added a project: LLVM.

`extsw` and `sldi` are supposed to combined if they are in them same BB in instruction selection phase. This patch handles the case where `extsw` and `sldi` are not in the same BB.


Repository:
  rL LLVM

https://reviews.llvm.org/D63806

Files:
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll

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