[PATCH] D63520: correct SILowerI1Copies for vgprs

[David Salinas via Phabricator via llvm-commits]

david-salinas updated this revision to Diff 206543.
david-salinas marked an inline comment as done.
david-salinas added a comment.

original fix was incorrect.  This update forces the RegClass if the destination operand is VReg_1, to SReg_32.  And then removes the attempt to change the new MI Operand(1).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63520/new/

https://reviews.llvm.org/D63520

Files:
  lib/Target/AMDGPU/SILowerI1Copies.cpp


Index: lib/Target/AMDGPU/SILowerI1Copies.cpp
===================================================================
--- lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -657,9 +656,6 @@
       unsigned SrcReg = MI.getOperand(1).getReg();
       assert(!MI.getOperand(1).getSubReg());
 
-      if (MRI->getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
-    	  MRI->setRegClass(SrcReg, &AMDGPU::SReg_32RegClass);
-
       if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
           !isLaneMaskReg(SrcReg)) {
         assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32);
@@ -667,7 +663,7 @@
         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
             .addReg(SrcReg)
             .addImm(0);
-      //  MI.getOperand(1).setReg(TmpReg);
+        MI.getOperand(1).setReg(TmpReg);
         SrcReg = TmpReg;
       }
 


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