[PATCH] D63665: [X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL364333: [X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't… (authored by ctopper, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D63665?vs=206061&id=206478#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63665/new/

https://reviews.llvm.org/D63665

Files:
  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
  llvm/trunk/lib/Target/X86/X86InstrAVX512.td
  llvm/trunk/lib/Target/X86/X86InstrSSE.td
  llvm/trunk/test/CodeGen/X86/vector-zmov.ll

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