[PATCH] D60708: [ARM] Code-generation infrastructure for MVE.

Simon Tatham via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 25 08:11:06 PDT 2019


simon_tatham updated this revision to Diff 206454.
simon_tatham added a comment.

Revised this patch to work properly with all the other MVE-related changes we've been making.

In particular, I've incorporated the whole of D63252 <https://reviews.llvm.org/D63252> into this patch, because after I added a RUN line to the new `mve-basic.ll` test to try it in integer-only MVE, I found the bitconvert selection patterns from that patch were needed to get it to pass.

A few other changes: I made all the vector types legal even in integer-only MVE (in that you can load, store and bitconvert them, but nothing else), which is necessary so that the calling convention can work (since it converts everything to `v2f64`, so that has to be legal!). I added a missing case in `copyPhysReg`, which I had previously switched from the NEON `VORRq` instruction to `MVE_VORR` for the purposes of copying a //single// q-reg, but forgot to do the same for copying multiple q-regs (the `QQPR` or `QQQQPR` reg classes). Integer MVE support also needed me to legalise the scalar FP types, so I changed the existing condition for that to `hasFPRegs` in place of `hasVFP2Base`, which had knock-on effects on a couple of existing tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60708/new/

https://reviews.llvm.org/D60708

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/test/CodeGen/ARM/fast-isel-call.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/no-fpu.ll
  llvm/test/CodeGen/Thumb2/mve-basic.ll
  llvm/test/CodeGen/Thumb2/mve-bitcasts.ll

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