[llvm] r364292 - [ARM] Add remaining miscellaneous MVE instructions.
Simon Tatham via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 04:24:33 PDT 2019
Author: statham
Date: Tue Jun 25 04:24:33 2019
New Revision: 364292
URL: http://llvm.org/viewvc/llvm-project?rev=364292&view=rev
Log:
[ARM] Add remaining miscellaneous MVE instructions.
This final batch includes the tail-predicated versions of the
low-overhead loop instructions (LETP); the VPSEL instruction to select
between two vector registers based on the predicate mask without
having to open a VPT block; and VPNOT which complements the predicate
mask in place.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62681
Added:
llvm/trunk/test/MC/ARM/mve-misc.s (with props)
llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt (with props)
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=364292&r1=364291&r2=364292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Tue Jun 25 04:24:33 2019
@@ -3895,3 +3895,106 @@ def MVE_VPST : MVE_MI<(outs ), (ins vpt_
let Defs = [P0];
}
+
+def MVE_VPSEL : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+ "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
+ bits<4> Qn;
+ bits<4> Qd;
+ bits<4> Qm;
+
+ let Inst{28} = 0b1;
+ let Inst{25-23} = 0b100;
+ let Inst{22} = Qd{3};
+ let Inst{21-20} = 0b11;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = 0b1;
+ let Inst{15-13} = Qd{2-0};
+ let Inst{12-9} = 0b0111;
+ let Inst{8} = 0b1;
+ let Inst{7} = Qn{3};
+ let Inst{6} = 0b0;
+ let Inst{5} = Qm{3};
+ let Inst{4} = 0b0;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = 0b1;
+}
+
+foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
+ "i8", "i16", "i32", "f16", "f32"] in
+def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
+ (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+
+def MVE_VPNOT : MVE_p<(outs), (ins), NoItinerary,
+ "vpnot", "", "", vpred_n, "", []> {
+ let Inst{31-0} = 0b11111110001100010000111101001101;
+ let Unpredictable{19-17} = 0b111;
+ let Unpredictable{12} = 0b1;
+ let Unpredictable{7} = 0b1;
+ let Unpredictable{5} = 0b1;
+ let Defs = [P0];
+ let Uses = [P0];
+
+ let Constraints = "";
+}
+
+class MVE_loltp_start<dag iops, string asm, string ops, bits<2> size>
+ : t2LOL<(outs GPRlr:$LR), iops, asm, ops> {
+ bits<4> Rn;
+ let Predicates = [HasMVEInt];
+ let Inst{22} = 0b0;
+ let Inst{21-20} = size;
+ let Inst{19-16} = Rn{3-0};
+ let Inst{12} = 0b0;
+}
+
+class MVE_DLSTP<string asm, bits<2> size>
+ : MVE_loltp_start<(ins rGPR:$Rn), asm, "$LR, $Rn", size> {
+ let Inst{13} = 0b1;
+ let Inst{11-1} = 0b00000000000;
+ let Unpredictable{10-1} = 0b1111111111;
+}
+
+class MVE_WLSTP<string asm, bits<2> size>
+ : MVE_loltp_start<(ins rGPR:$Rn, wlslabel_u11:$label),
+ asm, "$LR, $Rn, $label", size> {
+ bits<11> label;
+ let Inst{13} = 0b0;
+ let Inst{11} = label{0};
+ let Inst{10-1} = label{10-1};
+}
+
+def MVE_DLSTP_8 : MVE_DLSTP<"dlstp.8", 0b00>;
+def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
+def MVE_DLSTP_32 : MVE_DLSTP<"dlstp.32", 0b10>;
+def MVE_DLSTP_64 : MVE_DLSTP<"dlstp.64", 0b11>;
+
+def MVE_WLSTP_8 : MVE_WLSTP<"wlstp.8", 0b00>;
+def MVE_WLSTP_16 : MVE_WLSTP<"wlstp.16", 0b01>;
+def MVE_WLSTP_32 : MVE_WLSTP<"wlstp.32", 0b10>;
+def MVE_WLSTP_64 : MVE_WLSTP<"wlstp.64", 0b11>;
+
+class MVE_loltp_end<dag oops, dag iops, string asm, string ops>
+ : t2LOL<oops, iops, asm, ops> {
+ let Predicates = [HasMVEInt];
+ let Inst{22-21} = 0b00;
+ let Inst{19-16} = 0b1111;
+ let Inst{12} = 0b0;
+}
+
+def MVE_LETP : MVE_loltp_end<(outs GPRlr:$LRout),
+ (ins GPRlr:$LRin, lelabel_u11:$label),
+ "letp", "$LRin, $label"> {
+ bits<11> label;
+ let Inst{20} = 0b1;
+ let Inst{13} = 0b0;
+ let Inst{11} = label{0};
+ let Inst{10-1} = label{10-1};
+}
+
+def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
+ let Inst{20} = 0b0;
+ let Inst{13} = 0b1;
+ let Inst{11-1} = 0b00000000000;
+ let Unpredictable{21-20} = 0b11;
+ let Unpredictable{11-1} = 0b11111111111;
+}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=364292&r1=364291&r2=364292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 25 04:24:33 2019
@@ -372,8 +372,27 @@ def bflabel_u4 : BFLabelOp<"false", "fa
def bflabel_s12 : BFLabelOp<"true", "false", "12", "ARM::fixup_bfc_target">;
def bflabel_s16 : BFLabelOp<"true", "false", "16", "ARM::fixup_bf_target">;
def bflabel_s18 : BFLabelOp<"true", "false", "18", "ARM::fixup_bfl_target">;
-def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls">;
-def lelabel_u11 : BFLabelOp<"false", "true", "11", "ARM::fixup_le">;
+
+def wlslabel_u11_asmoperand : AsmOperandClass {
+ let Name = "WLSLabel";
+ let RenderMethod = "addImmOperands";
+ let PredicateMethod = "isUnsignedOffset<11, 1>";
+ let DiagnosticString =
+ "loop end is out of range or not a positive multiple of 2";
+}
+def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls"> {
+ let ParserMatchClass = wlslabel_u11_asmoperand;
+}
+def lelabel_u11_asmoperand : AsmOperandClass {
+ let Name = "LELabel";
+ let RenderMethod = "addImmOperands";
+ let PredicateMethod = "isLEOffset";
+ let DiagnosticString =
+ "loop start is out of range or not a negative multiple of 2";
+}
+def lelabel_u11 : BFLabelOp<"false", "true", "11", "ARM::fixup_le"> {
+ let ParserMatchClass = lelabel_u11_asmoperand;
+}
def bfafter_target : Operand<OtherVT> {
let EncoderMethod = "getBFAfterTargetOpValue";
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=364292&r1=364291&r2=364292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jun 25 04:24:33 2019
@@ -1013,6 +1013,18 @@ public:
return false;
}
+ // checks whether this operand is an offset suitable for the LE /
+ // LETP instructions in Arm v8.1M
+ bool isLEOffset() const {
+ if (!isImm()) return false;
+ if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
+ if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Val = CE->getValue();
+ return Val < 0 && Val >= -4094 && (Val & 1) == 0;
+ }
+ return false;
+ }
+
// checks whether this operand is a memory operand computed as an offset
// applied to PC. the offset may have 8 bits of magnitude and is represented
// with two bits of shift. textually it may be either [pc, #imm], #imm or
@@ -6213,6 +6225,7 @@ StringRef ARMAsmParser::splitMnemonic(St
Mnemonic == "vmule" || Mnemonic == "vmult" ||
Mnemonic == "vrintne" ||
Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
+ Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
Mnemonic.startswith("vq")))) {
unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
if (CC != ~0U) {
@@ -6261,7 +6274,7 @@ StringRef ARMAsmParser::splitMnemonic(St
Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
- Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
+ Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
if (CC != ~0U) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
@@ -6337,7 +6350,9 @@ void ARMAsmParser::getMnemonicAcceptInfo
Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
(hasMVE() &&
(Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
- Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) {
+ Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
+ Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
+ Mnemonic.startswith("letp")))) {
// These mnemonics are never predicable
CanAcceptPredicationCode = false;
} else if (!isThumb()) {
@@ -6599,7 +6614,7 @@ bool ARMAsmParser::shouldOmitVectorPredi
Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
return true;
- if (Mnemonic.startswith("vctp"))
+ if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
return false;
if (Mnemonic.startswith("vmov") &&
@@ -7742,22 +7757,6 @@ bool ARMAsmParser::validateInstruction(M
"code specified");
break;
}
- case ARM::t2WLS: {
- int idx = Opcode == ARM::t2WLS ? 3 : 4;
- if (!static_cast<ARMOperand &>(*Operands[idx]).isUnsignedOffset<11, 1>())
- return Error(Operands[idx]->getStartLoc(),
- "loop end is out of range or not a positive multiple of 2");
- break;
- }
- case ARM::t2LEUpdate: {
- if (Inst.getOperand(2).isImm() &&
- !(Inst.getOperand(2).getImm() < 0 &&
- Inst.getOperand(2).getImm() >= -4094 &&
- (Inst.getOperand(2).getImm() & 1) == 0))
- return Error(Operands[2]->getStartLoc(),
- "loop start is out of range or not a negative multiple of 2");
- break;
- }
case ARM::t2BFi:
case ARM::t2BFr:
case ARM::t2BFLi:
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=364292&r1=364291&r2=364292&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Jun 25 04:24:33 2019
@@ -5948,10 +5948,14 @@ static DecodeStatus DecodeLOLoop(MCInst
const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
+ if (Inst.getOpcode() == ARM::MVE_LCTP)
+ return S;
+
unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
fieldFromInstruction(Insn, 1, 10) << 1;
switch (Inst.getOpcode()) {
case ARM::t2LEUpdate:
+ case ARM::MVE_LETP:
Inst.addOperand(MCOperand::createReg(ARM::LR));
Inst.addOperand(MCOperand::createReg(ARM::LR));
LLVM_FALLTHROUGH;
@@ -5961,6 +5965,10 @@ static DecodeStatus DecodeLOLoop(MCInst
return MCDisassembler::Fail;
break;
case ARM::t2WLS:
+ case ARM::MVE_WLSTP_8:
+ case ARM::MVE_WLSTP_16:
+ case ARM::MVE_WLSTP_32:
+ case ARM::MVE_WLSTP_64:
Inst.addOperand(MCOperand::createReg(ARM::LR));
if (!Check(S,
DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
@@ -5970,9 +5978,22 @@ static DecodeStatus DecodeLOLoop(MCInst
return MCDisassembler::Fail;
break;
case ARM::t2DLS:
+ case ARM::MVE_DLSTP_8:
+ case ARM::MVE_DLSTP_16:
+ case ARM::MVE_DLSTP_32:
+ case ARM::MVE_DLSTP_64:
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
if (Rn == 0xF) {
- return MCDisassembler::Fail;
+ // Enforce all the rest of the instruction bits in LCTP, which
+ // won't have been reliably checked based on LCTP's own tablegen
+ // record, because we came to this decode by a roundabout route.
+ uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
+ if ((Insn & ~SBZMask) != CanonicalLCTP)
+ return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
+ if (Insn != CanonicalLCTP)
+ Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
+
+ Inst.setOpcode(ARM::MVE_LCTP);
} else {
Inst.addOperand(MCOperand::createReg(ARM::LR));
if (!Check(S, DecoderGPRRegisterClass(Inst,
Added: llvm/trunk/test/MC/ARM/mve-misc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-misc.s?rev=364292&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-misc.s (added)
+++ llvm/trunk/test/MC/ARM/mve-misc.s Tue Jun 25 04:24:33 2019
@@ -0,0 +1,176 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t
+# RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
+
+# CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+vpsel q0, q5, q2
+
+# CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+vpnot
+
+# CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r0, #1668
+
+# CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.16 lr, r0, #1668
+
+# CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.32 lr, r4, #2706
+
+# CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.64 lr, lr, #3026
+
+# CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r5, #3436
+
+# CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.16 lr, r1, #1060
+
+# CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.32 lr, r7, #4036
+
+# CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r1, #538
+
+# CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #1404
+
+# CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #1408
+
+# CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #2358
+
+# CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #4086
+
+# CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r11, #1442
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #1443
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r10, #4096
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, sp, #1442
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.16 lr, sp, #1442
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.32 r10, r11, #1442
+
+# CHECK: wlstp.8 lr, r1, .Lendloop @ encoding: [0x01'A',0xf0'A',0x01'A',0xc0'A']
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.8 lr, r1, .Lendloop
+
+# CHECK: wlstp.16 lr, r2, .Lendloop @ encoding: [0x12'A',0xf0'A',0x01'A',0xc0'A']
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.16 lr, r2, .Lendloop
+
+# CHECK: wlstp.32 lr, r3, .Lendloop @ encoding: [0x23'A',0xf0'A',0x01'A',0xc0'A']
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.32 lr, r3, .Lendloop
+
+# CHECK: wlstp.64 lr, r5, .Lendloop @ encoding: [0x35'A',0xf0'A',0x01'A',0xc0'A']
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.64 lr, r5, .Lendloop
+
+# CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.8 lr, r5
+
+# CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.16 lr, r5
+
+# CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.32 lr, r7
+
+# CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.64 lr, r2
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.64 lr, sp
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.64 r10, r0
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+dlstp.64 lr, pc
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, #-2
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, #-8
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, #-4094
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp r0, #-8
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, #8
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, #-4096
+
+# CHECK: letp lr, .Lstartloop @ encoding: [0x1f'A',0xf0'A',0x01'A',0xc0'A']
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+letp lr, .Lstartloop
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: instruction requires: mve
+lctp
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+it eq
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: instruction requires: mve
+lctpeq
+
+vpste
+vpselt.s16 q0, q1, q2
+vpsele.i32 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
Propchange: llvm/trunk/test/MC/ARM/mve-misc.s
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/ARM/mve-misc.s
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
Added: llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt?rev=364292&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt Tue Jun 25 04:24:33 2019
@@ -0,0 +1,111 @@
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vpsel q0, q5, q2 @ encoding: [0x3b,0xfe,0x05,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x05,0x0f]
+
+# CHECK: vpnot @ encoding: [0x31,0xfe,0x4d,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x0f]
+
+# CHECK: wlstp.8 lr, r0, #1668 @ encoding: [0x00,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x00,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.16 lr, r0, #1668 @ encoding: [0x10,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.32 lr, r4, #2706 @ encoding: [0x24,0xf0,0x49,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x24,0xf0,0x49,0xcd]
+
+# CHECK: wlstp.64 lr, lr, #3026 @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x3e,0xf0,0xe9,0xcd]
+
+# CHECK: wlstp.8 lr, r5, #3436 @ encoding: [0x05,0xf0,0xb7,0xc6]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0xb7,0xc6]
+
+# CHECK: wlstp.16 lr, r1, #1060 @ encoding: [0x11,0xf0,0x13,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x11,0xf0,0x13,0xc2]
+
+# CHECK: wlstp.32 lr, r7, #4036 @ encoding: [0x27,0xf0,0xe3,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0xe3,0xc7]
+
+# CHECK: wlstp.8 lr, r1, #538 @ encoding: [0x01,0xf0,0x0d,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x01,0xf0,0x0d,0xc9]
+
+# CHECK: wlstp.8 lr, r10, #1404 @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xbf,0xc2]
+
+# CHECK: wlstp.8 lr, r10, #1408 @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xc1,0xc2]
+
+# CHECK: wlstp.8 lr, r10, #2358 @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0x9b,0xcc]
+
+# CHECK: wlstp.8 lr, r10, #4086 @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xfb,0xcf]
+
+# CHECK: wlstp.8 lr, r11, #1442 @ encoding: [0x0b,0xf0,0xd1,0xca]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0b,0xf0,0xd1,0xca]
+
+# CHECK: dlstp.8 lr, r5 @ encoding: [0x05,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.16 lr, r5 @ encoding: [0x15,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x15,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.32 lr, r7 @ encoding: [0x27,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.64 lr, r2 @ encoding: [0x32,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x32,0xf0,0x01,0xe0]
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xc8]
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x05,0xc0]
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0xff,0xcf]
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x4f,0xf0,0x01,0xe0]
+
+# The following tests have to go last because of the NOMVE-NOT checks.
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOMVE: it eq @ encoding: [0x08,0xbf]
+[0x08,0xbf]
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+[0x0f,0xf0,0x01,0xe0]
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
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