[llvm] r364262 - AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Jun 24 18:07:22 2019
New Revision: 364262

URL: http://llvm.org/viewvc/llvm-project?rev=364262&view=rev
Log:
AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=364262&r1=364261&r2=364262&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Mon Jun 24 18:07:22 2019
@@ -1503,12 +1503,16 @@ AMDGPURegisterBankInfo::getInstrMapping(
       break;
     }
     case Intrinsic::amdgcn_class: {
-      unsigned SrcReg = MI.getOperand(2).getReg();
-      unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
+      unsigned Src0Reg = MI.getOperand(2).getReg();
+      unsigned Src1Reg = MI.getOperand(3).getReg();
+      unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits();
+      unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits();
       unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
       OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize);
-      OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(SrcReg, MRI, *TRI),
-                                               SrcSize);
+      OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(Src0Reg, MRI, *TRI),
+                                               Src0Size);
+      OpdsMapping[3] = AMDGPU::getValueMapping(getRegBankID(Src1Reg, MRI, *TRI),
+                                               Src1Size);
       break;
     }
     }

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir?rev=364262&r1=364261&r2=364262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir Mon Jun 24 18:07:22 2019
@@ -3,29 +3,66 @@
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: class_s
+name: class_ss
 legalized: true
 
 body: |
   bb.0:
-    liveins: $sgpr0
-    ; CHECK-LABEL: name: class_s
-    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
-    %0:_(s32) = COPY $sgpr0
-    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+    liveins: $sgpr0_sgpr1, $sgpr2
+    ; CHECK-LABEL: name: class_ss
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32) = COPY $sgpr2
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 ...
 
 ---
-name: class_v
+name: class_sv
 legalized: true
 
 body: |
   bb.0:
-    liveins: $vgpr0
-    ; CHECK-LABEL: name: class_v
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+    liveins: $sgpr0_sgpr1, $vgpr0
+
+    ; CHECK-LABEL: name: class_sv
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32) = COPY $vgpr0
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
+...
+
+---
+name: class_vs
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $sgpr0
+    ; CHECK-LABEL: name: class_vs
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = COPY $sgpr0
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
+...
+
+---
+name: class_vv
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: class_vv
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = COPY $vgpr2
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 ...