[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

[Piotr Sobczak via Phabricator via llvm-commits]

piotr marked an inline comment as done.
piotr added inline comments.


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Comment at: test/CodeGen/AMDGPU/mov-opt.ll:14
+
+define void @mov_opt(i32 inreg, i32 inreg, <4 x i32> inreg, i32 inreg %inp1, i32 inreg %inp2, i32 inreg %inp3, i32 inreg, i32 inreg, i32 inreg, i32) local_unnamed_addr #5 {
+.entry:
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arsenm wrote:
> arsenm wrote:
> > You should be able to reduce this more
> I don't actually see any redundant constants?
The move constants are by-products of different phi nodes and this is why they are not explicitly written in the IR. They get created during the isel in HandlePHINodesInSuccessorBlocks. 

I will work on simplifying the IR test case even more. 


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63709/new/

https://reviews.llvm.org/D63709