[llvm] r364221 - [CodeGen] Add missing vector type legalization for ctlz_zero_undef
Roland Froese via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 24 12:27:07 PDT 2019
Author: froese
Date: Mon Jun 24 12:27:07 2019
New Revision: 364221
URL: http://llvm.org/viewvc/llvm-project?rev=364221&view=rev
Log:
[CodeGen] Add missing vector type legalization for ctlz_zero_undef
Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as
ctlz and cttz.
Differential Revision: https://reviews.llvm.org/D63463
Added:
llvm/trunk/test/CodeGen/X86/vec_clz.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/test/CodeGen/PowerPC/vec_clz.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=364221&r1=364220&r2=364221&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Jun 24 12:27:07 2019
@@ -2829,8 +2829,10 @@ void DAGTypeLegalizer::WidenVectorResult
case ISD::BITREVERSE:
case ISD::BSWAP:
case ISD::CTLZ:
+ case ISD::CTLZ_ZERO_UNDEF:
case ISD::CTPOP:
case ISD::CTTZ:
+ case ISD::CTTZ_ZERO_UNDEF:
case ISD::FNEG:
case ISD::FCANONICALIZE:
Res = WidenVecRes_Unary(N);
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_clz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_clz.ll?rev=364221&r1=364220&r2=364221&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_clz.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_clz.ll Mon Jun 24 12:27:07 2019
@@ -1,6 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Check the vctlz* instructions that were added in P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone
@@ -8,33 +9,95 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone
define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone {
+; CHECK-LABEL: test_v16i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclzb 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: test_v16i8:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vclzb 2, 2
+; CHECK-NOVSX-NEXT: blr
%vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x)
ret <16 x i8> %vcnt
-; CHECK: @test_v16i8
-; CHECK: vclzb 2, 2
-; CHECK: blr
}
define <8 x i16> @test_v8i16(<8 x i16> %x) nounwind readnone {
+; CHECK-LABEL: test_v8i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclzh 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: test_v8i16:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vclzh 2, 2
+; CHECK-NOVSX-NEXT: blr
%vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x)
ret <8 x i16> %vcnt
-; CHECK: @test_v8i16
-; CHECK: vclzh 2, 2
-; CHECK: blr
}
define <4 x i32> @test_v4i32(<4 x i32> %x) nounwind readnone {
+; CHECK-LABEL: test_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclzw 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: test_v4i32:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vclzw 2, 2
+; CHECK-NOVSX-NEXT: blr
%vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x)
ret <4 x i32> %vcnt
-; CHECK: @test_v4i32
-; CHECK: vclzw 2, 2
-; CHECK: blr
}
define <2 x i64> @test_v2i64(<2 x i64> %x) nounwind readnone {
+; CHECK-LABEL: test_v2i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclzd 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: test_v2i64:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vclzd 2, 2
+; CHECK-NOVSX-NEXT: blr
%vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x)
ret <2 x i64> %vcnt
-; CHECK: @test_v2i64
-; CHECK: vclzd 2, 2
-; CHECK: blr
+}
+
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1 immarg)
+
+define <2 x i32> @illegal_ctlz(<2 x i32> %v1) {
+; CHECK-LABEL: illegal_ctlz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vclzw 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: illegal_ctlz:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vclzw 2, 2
+; CHECK-NOVSX-NEXT: blr
+ %v2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %v1, i1 true)
+ ret <2 x i32> %v2
+}
+
+declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1 immarg)
+
+define <2 x i32> @illegal_cttz(<2 x i32> %v1) {
+; CHECK-LABEL: illegal_cttz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vspltisw 3, 1
+; CHECK-NEXT: vsubuwm 3, 2, 3
+; CHECK-NEXT: xxlandc 34, 35, 34
+; CHECK-NEXT: vpopcntw 2, 2
+; CHECK-NEXT: blr
+;
+; CHECK-NOVSX-LABEL: illegal_cttz:
+; CHECK-NOVSX: # %bb.0:
+; CHECK-NOVSX-NEXT: vspltisw 3, 1
+; CHECK-NOVSX-NEXT: vsubuwm 3, 2, 3
+; CHECK-NOVSX-NEXT: vandc 2, 3, 2
+; CHECK-NOVSX-NEXT: vpopcntw 2, 2
+; CHECK-NOVSX-NEXT: blr
+ %v2 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %v1, i1 true)
+ ret <2 x i32> %v2
}
Added: llvm/trunk/test/CodeGen/X86/vec_clz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_clz.ll?rev=364221&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_clz.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_clz.ll Mon Jun 24 12:27:07 2019
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -x86-experimental-vector-widening-legalization | FileCheck %s
+
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1 immarg)
+
+define <2 x i32> @illegal_ctlz(<2 x i32> %v1) {
+; CHECK-LABEL: illegal_ctlz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrld $1, %xmm1
+; CHECK-NEXT: por %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: psrld $2, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrld $4, %xmm1
+; CHECK-NEXT: por %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: psrld $8, %xmm0
+; CHECK-NEXT: por %xmm1, %xmm0
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrld $16, %xmm1
+; CHECK-NEXT: por %xmm0, %xmm1
+; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
+; CHECK-NEXT: pxor %xmm1, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: psrlw $1, %xmm0
+; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: psubb %xmm0, %xmm2
+; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
+; CHECK-NEXT: movdqa %xmm2, %xmm1
+; CHECK-NEXT: pand %xmm0, %xmm1
+; CHECK-NEXT: psrlw $2, %xmm2
+; CHECK-NEXT: pand %xmm0, %xmm2
+; CHECK-NEXT: paddb %xmm1, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: psrlw $4, %xmm0
+; CHECK-NEXT: paddb %xmm2, %xmm0
+; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: movdqa %xmm0, %xmm2
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; CHECK-NEXT: psadbw %xmm1, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: psadbw %xmm1, %xmm0
+; CHECK-NEXT: packuswb %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %v2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %v1, i1 true)
+ ret <2 x i32> %v2
+}
+
+declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1 immarg)
+
+define <2 x i32> @illegal_cttz(<2 x i32> %v1) {
+; CHECK-LABEL: illegal_cttz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT: paddd %xmm0, %xmm1
+; CHECK-NEXT: pandn %xmm1, %xmm0
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrlw $1, %xmm1
+; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: psubb %xmm1, %xmm0
+; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
+; CHECK-NEXT: movdqa %xmm0, %xmm2
+; CHECK-NEXT: pand %xmm1, %xmm2
+; CHECK-NEXT: psrlw $2, %xmm0
+; CHECK-NEXT: pand %xmm1, %xmm0
+; CHECK-NEXT: paddb %xmm2, %xmm0
+; CHECK-NEXT: movdqa %xmm0, %xmm1
+; CHECK-NEXT: psrlw $4, %xmm1
+; CHECK-NEXT: paddb %xmm0, %xmm1
+; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
+; CHECK-NEXT: pxor %xmm0, %xmm0
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; CHECK-NEXT: psadbw %xmm0, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; CHECK-NEXT: psadbw %xmm0, %xmm1
+; CHECK-NEXT: packuswb %xmm2, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %v2 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %v1, i1 true)
+ ret <2 x i32> %v2
+}
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