[llvm] r364208 - [AMDGPU] Allow any value in unused src0 field in v_nop

[Tim Renouf via llvm-commits]

Author: tpr
Date: Mon Jun 24 10:35:20 2019
New Revision: 364208

URL: http://llvm.org/viewvc/llvm-project?rev=364208&view=rev
Log:
[AMDGPU] Allow any value in unused src0 field in v_nop

Summary:
The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.

Differential Revision: https://reviews.llvm.org/D63724

Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f

Modified:
    llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
    llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt
    llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt
    llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt

Modified: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td?rev=364208&r1=364207&r2=364208&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td Mon Jun 24 10:35:20 2019
@@ -14,7 +14,7 @@ class VOP1e <bits<8> op, VOPProfile P> :
   bits<8> vdst;
   bits<9> src0;
 
-  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, 0);
+  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, ?);
   let Inst{16-9}  = op;
   let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
   let Inst{31-25} = 0x3f; //encoding

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt?rev=364208&r1=364207&r2=364208&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt Mon Jun 24 10:35:20 2019
@@ -2,3 +2,6 @@
 
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
+
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt?rev=364208&r1=364207&r2=364208&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt Mon Jun 24 10:35:20 2019
@@ -3,6 +3,9 @@
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # CHECK: v_clrexcp                       ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt?rev=364208&r1=364207&r2=364208&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt Mon Jun 24 10:35:20 2019
@@ -6,6 +6,9 @@
 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e