[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D63709#1555766 <https://reviews.llvm.org/D63709#1555766>, @piotr wrote:

> This opt opportunity presents itself after the register coalescer, where inline constants are moved to the same registers (attaching IR example testcase imminently). MachineCSE is run too early to spot this and the last occurence of si-shrink-instructions is run at the right time. I think, for similar reasons some other peepholes were also placed in this pass, even though they are not about 32-bit encoding.


I'd like to take a look a more reduced testcase. My intuition is something else is going wrong that's not eliminating this



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Comment at: test/CodeGen/AMDGPU/mov-opt.ll:14
+
+define void @mov_opt(i32 inreg, i32 inreg, <4 x i32> inreg, i32 inreg %inp1, i32 inreg %inp2, i32 inreg %inp3, i32 inreg, i32 inreg, i32 inreg, i32) local_unnamed_addr #5 {
+.entry:
----------------
You should be able to reduce this more


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63709/new/

https://reviews.llvm.org/D63709