[PATCH] D63724: [AMDGPU] Allow any value in unused src0 field in v_nop

Tim Renouf via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 24 09:27:04 PDT 2019


tpr created this revision.
Herald added subscribers: llvm-commits, t-tye, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.

The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.

Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f


Repository:
  rL LLVM

https://reviews.llvm.org/D63724

Files:
  lib/Target/AMDGPU/VOP1Instructions.td
  test/MC/Disassembler/AMDGPU/nop.txt
  test/MC/Disassembler/AMDGPU/vop1.txt
  test/MC/Disassembler/AMDGPU/vop1_vi.txt


Index: test/MC/Disassembler/AMDGPU/vop1_vi.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/vop1_vi.txt
+++ test/MC/Disassembler/AMDGPU/vop1_vi.txt
@@ -6,6 +6,9 @@
 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 
Index: test/MC/Disassembler/AMDGPU/vop1.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/vop1.txt
+++ test/MC/Disassembler/AMDGPU/vop1.txt
@@ -3,6 +3,9 @@
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # CHECK: v_clrexcp                       ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 
Index: test/MC/Disassembler/AMDGPU/nop.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/nop.txt
+++ test/MC/Disassembler/AMDGPU/nop.txt
@@ -2,3 +2,6 @@
 
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
+
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
Index: lib/Target/AMDGPU/VOP1Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP1Instructions.td
+++ lib/Target/AMDGPU/VOP1Instructions.td
@@ -14,7 +14,7 @@
   bits<8> vdst;
   bits<9> src0;
 
-  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, 0);
+  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, ?);
   let Inst{16-9}  = op;
   let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
   let Inst{31-25} = 0x3f; //encoding


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