[llvm] r364188 - Hexagon: Rename Register class
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 24 08:27:29 PDT 2019
Author: arsenm
Date: Mon Jun 24 08:27:29 2019
New Revision: 364188
URL: http://llvm.org/viewvc/llvm-project?rev=364188&view=rev
Log:
Hexagon: Rename Register class
This avoids a naming conflict in a future patch.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=364188&r1=364187&r2=364188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Mon Jun 24 08:27:29 2019
@@ -45,17 +45,18 @@ namespace llvm {
namespace {
- struct Register {
+ // FIXME: Use TargetInstrInfo::RegSubRegPair
+ struct RegisterSubReg {
unsigned R, S;
- Register(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
- Register(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
+ RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
+ RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
- bool operator== (const Register &Reg) const {
+ bool operator== (const RegisterSubReg &Reg) const {
return R == Reg.R && S == Reg.S;
}
- bool operator< (const Register &Reg) const {
+ bool operator< (const RegisterSubReg &Reg) const {
return R < Reg.R || (R == Reg.R && S < Reg.S);
}
};
@@ -63,10 +64,10 @@ namespace {
struct PrintRegister {
friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
- PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
+ PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
private:
- Register Reg;
+ RegisterSubReg Reg;
const TargetRegisterInfo &TRI;
};
@@ -98,8 +99,8 @@ namespace {
private:
using VectOfInst = SetVector<MachineInstr *>;
- using SetOfReg = std::set<Register>;
- using RegToRegMap = std::map<Register, Register>;
+ using SetOfReg = std::set<RegisterSubReg>;
+ using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>;
const HexagonInstrInfo *TII = nullptr;
const HexagonRegisterInfo *TRI = nullptr;
@@ -110,12 +111,12 @@ namespace {
bool isPredReg(unsigned R);
void collectPredicateGPR(MachineFunction &MF);
- void processPredicateGPR(const Register &Reg);
+ void processPredicateGPR(const RegisterSubReg &Reg);
unsigned getPredForm(unsigned Opc);
bool isConvertibleToPredForm(const MachineInstr *MI);
bool isScalarCmp(unsigned Opc);
- bool isScalarPred(Register PredReg);
- Register getPredRegFor(const Register &Reg);
+ bool isScalarPred(RegisterSubReg PredReg);
+ RegisterSubReg getPredRegFor(const RegisterSubReg &Reg);
bool convertToPredForm(MachineInstr *MI);
bool eliminatePredCopies(MachineFunction &MF);
};
@@ -210,7 +211,7 @@ void HexagonGenPredicate::collectPredica
case Hexagon::C2_tfrpr:
case TargetOpcode::COPY:
if (isPredReg(MI->getOperand(1).getReg())) {
- Register RD = MI->getOperand(0);
+ RegisterSubReg RD = MI->getOperand(0);
if (TargetRegisterInfo::isVirtualRegister(RD.R))
PredGPRs.insert(RD);
}
@@ -220,7 +221,7 @@ void HexagonGenPredicate::collectPredica
}
}
-void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
+void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) {
LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n");
using use_iterator = MachineRegisterInfo::use_iterator;
@@ -239,7 +240,7 @@ void HexagonGenPredicate::processPredica
}
}
-Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
+RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
// Create a predicate register for a given Reg. The newly created register
// will have its value copied from Reg, so that it can be later used as
// an operand in other instructions.
@@ -254,7 +255,7 @@ Register HexagonGenPredicate::getPredReg
unsigned Opc = DefI->getOpcode();
if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) {
assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
- Register PR = DefI->getOperand(1);
+ RegisterSubReg PR = DefI->getOperand(1);
G2P.insert(std::make_pair(Reg, PR));
LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
return PR;
@@ -271,10 +272,10 @@ Register HexagonGenPredicate::getPredReg
MachineBasicBlock::iterator DefIt = DefI;
BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
.addReg(Reg.R, 0, Reg.S);
- G2P.insert(std::make_pair(Reg, Register(NewPR)));
- LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI)
+ G2P.insert(std::make_pair(Reg, RegisterSubReg(NewPR)));
+ LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegisterSubReg(NewPR), *TRI)
<< '\n');
- return Register(NewPR);
+ return RegisterSubReg(NewPR);
}
llvm_unreachable("Invalid argument");
@@ -316,12 +317,12 @@ bool HexagonGenPredicate::isScalarCmp(un
return false;
}
-bool HexagonGenPredicate::isScalarPred(Register PredReg) {
- std::queue<Register> WorkQ;
+bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) {
+ std::queue<RegisterSubReg> WorkQ;
WorkQ.push(PredReg);
while (!WorkQ.empty()) {
- Register PR = WorkQ.front();
+ RegisterSubReg PR = WorkQ.front();
WorkQ.pop();
const MachineInstr *DefI = MRI->getVRegDef(PR.R);
if (!DefI)
@@ -350,7 +351,7 @@ bool HexagonGenPredicate::isScalarPred(R
// Add operands to the queue.
for (const MachineOperand &MO : DefI->operands())
if (MO.isReg() && MO.isUse())
- WorkQ.push(Register(MO.getReg()));
+ WorkQ.push(RegisterSubReg(MO.getReg()));
break;
// All non-vector compares are ok, everything else is bad.
@@ -372,7 +373,7 @@ bool HexagonGenPredicate::convertToPredF
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
- Register Reg(MO);
+ RegisterSubReg Reg(MO);
if (Reg.S && Reg.S != Hexagon::isub_lo)
return false;
if (!PredGPRs.count(Reg))
@@ -399,7 +400,7 @@ bool HexagonGenPredicate::convertToPredF
// If it's a scalar predicate register, then all bits in it are
// the same. Otherwise, to determine whether all bits are 0 or not
// we would need to use any8.
- Register PR = getPredRegFor(MI->getOperand(1));
+ RegisterSubReg PR = getPredRegFor(MI->getOperand(1));
if (!isScalarPred(PR))
return false;
// This will skip the immediate argument when creating the predicate
@@ -410,19 +411,19 @@ bool HexagonGenPredicate::convertToPredF
// Some sanity: check that def is in operand #0.
MachineOperand &Op0 = MI->getOperand(0);
assert(Op0.isDef());
- Register OutR(Op0);
+ RegisterSubReg OutR(Op0);
// Don't use getPredRegFor, since it will create an association between
// the argument and a created predicate register (i.e. it will insert a
// copy if a new predicate register is created).
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
- Register NewPR = MRI->createVirtualRegister(PredRC);
+ RegisterSubReg NewPR = MRI->createVirtualRegister(PredRC);
MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
// Add predicate counterparts of the GPRs.
for (unsigned i = 1; i < NumOps; ++i) {
- Register GPR = MI->getOperand(i);
- Register Pred = getPredRegFor(GPR);
+ RegisterSubReg GPR = MI->getOperand(i);
+ RegisterSubReg Pred = getPredRegFor(GPR);
MIB.addReg(Pred.R, 0, Pred.S);
}
LLVM_DEBUG(dbgs() << "generated: " << *MIB);
@@ -440,7 +441,7 @@ bool HexagonGenPredicate::convertToPredF
// then the output will be a predicate register. Do not visit the
// users of it.
if (!isPredReg(NewOutR)) {
- Register R(NewOutR);
+ RegisterSubReg R(NewOutR);
PredGPRs.insert(R);
processPredicateGPR(R);
}
@@ -467,8 +468,8 @@ bool HexagonGenPredicate::eliminatePredC
for (MachineInstr &MI : MBB) {
if (MI.getOpcode() != TargetOpcode::COPY)
continue;
- Register DR = MI.getOperand(0);
- Register SR = MI.getOperand(1);
+ RegisterSubReg DR = MI.getOperand(0);
+ RegisterSubReg SR = MI.getOperand(1);
if (!TargetRegisterInfo::isVirtualRegister(DR.R))
continue;
if (!TargetRegisterInfo::isVirtualRegister(SR.R))
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