[PATCH] D63715: AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: tstellar.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, kristof.beyls, rovka, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
to extend to the 32-bit half, and then to 64.

      

I'm not sure what the line should be between what RegBankSelect
handles, and what instruction select does, but for now I'm erring on
the side of RegBankSelect for future post-RBS combines.


https://reviews.llvm.org/D63715

Files:
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir

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