[PATCH] D63628: AMD K10 (Barcelona) Initial Scheduler model

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

(forgot to submit inline comments)



================
Comment at: lib/Target/X86/X86ScheduleBarcelona.td:185
+                         list<int> Res, int UOps> {
+  defm : BnWriteRes<SchedRW, !listconcat([IntScheduler], ExePorts),
+                    Lat, !listconcat([1], Res), UOps>;
----------------
javed.absar wrote:
> You can use 'listA # listB'  to concatenate to improve readability 
There isn't that much TableGen stuff here, i think keeping it as explicit as possible is best..


================
Comment at: lib/Target/X86/X86ScheduleBarcelona.td:760
+////////////////////////////////////////////////////////////////////////////////
+
+} // SchedModel
----------------
lebedev.ri wrote:
> courbet wrote:
> > Does K10 have any zeroing/dependency breaking idioms ? Maybe add a FIXME to implement them.
> Well, it's a good question.
> Agner says it does, but unless i'm doing something horribly wrong even the trivial `xor %eax, %eax` doesn't work.
> So i've left it for later.
I've added a FIXME note for now.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63628/new/

https://reviews.llvm.org/D63628