[PATCH] D63677: [ARM] Don't reserve R12 on Thumb1 as an emergency spill slot.

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 21 15:13:09 PDT 2019


efriedma created this revision.
efriedma added reviewers: dmgreen, t.p.northover, SjoerdMeijer.
Herald added subscribers: kristof.beyls, javed.absar, qcolombet.
Herald added a project: LLVM.

The current implementation of ThumbRegisterInfo::saveScavengerRegister is bad for two reasons: one, it's buggy, and two, it blocks using R12 <https://reviews.llvm.org/source/lldb/> for other optimizations.  So this patch gets rid of it, and adds the necessary support for using an ordinary emergency spill slot on Thumb1.

(Specifically, I think saveScavengerRegister was broken by r305625, and nobody noticed for two years because the codepath is almost never used. The new code will also probably not be used much, but it now has better tests, and if we fail to emit a necessary emergency spill slot we get a reasonable error message instead of a miscompile.)

A rough outline of the changes in the patch:

1. Gets rid of ThumbRegisterInfo::saveScavengerRegister.
2. Modifies ARMFrameLowering::determineCalleeSaves to allocate an emergency spill slot for Thumb1.
3. Implements useFPForScavengingIndex, so the emergency spill slot isn't placed at a negative offset from FP on Thumb1.
4. Modifies the heuristics for allocating an emergency spill slot to support Thumb1.  This includes fixing ExtraCSSpill so we don't try to use "lr" as a substitute for allocating an emergency spill slot.
5. Allocates a base pointer in more cases, so the emergency spill slot is always accessible.
6. Modifies ARMFrameLowering::ResolveFrameIndexReference to compute the right offset in the new cases where we're forcing a base pointer.
7. Ensures we never generate a load or store with an offset outside of its frame object.  This makes the heuristics more straightforward.

Some of the changes to the emergency spill slot heuristics in estimateRSStackSizeLimit and determineCalleeSaves affect ARM/Thumb2; hopefully, they should allow the compiler to avoid allocating an emergency spill slot in cases where it isn't necessary. The rest of the changes should only affect Thumb1.

As far as I can tell, there isn't any good way to split this patch. If we don't get rid of saveScavengerRegister, the other changes are essentially useless.  And if we get rid of saveScavengerRegister without the other fixes, we'll introduce bugs.  I'm open to suggestions about this, though.


Repository:
  rL LLVM

https://reviews.llvm.org/D63677

Files:
  lib/Target/ARM/ARMBaseRegisterInfo.cpp
  lib/Target/ARM/ARMFrameLowering.cpp
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ThumbRegisterInfo.cpp
  lib/Target/ARM/ThumbRegisterInfo.h
  test/CodeGen/ARM/ldrex-frame-size.ll
  test/CodeGen/ARM/scavenging.mir
  test/CodeGen/ARM/thumb1-varalloc.ll
  test/CodeGen/Thumb/emergency-spill-slot.ll
  test/CodeGen/Thumb/frame-access.ll
  test/CodeGen/Thumb/large-stack.ll

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