[llvm] r364068 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Jun 21 09:11:18 2019
New Revision: 364068

URL: http://llvm.org/viewvc/llvm-project?rev=364068&view=rev
Log:
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=364068&r1=364067&r2=364068&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Jun 21 09:11:18 2019
@@ -6148,7 +6148,7 @@ static DecodeStatus DecodePowerTwoOperan
   if (Val < MinLog || Val > MaxLog)
     return MCDisassembler::Fail;
 
-  Inst.addOperand(MCOperand::createImm(1 << Val));
+  Inst.addOperand(MCOperand::createImm(1LL << Val));
   return S;
 }