[PATCH] D56772: [MIR] Add simple PRE pass to MachineCSE

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev marked 2 inline comments as done.
anton-afanasyev added inline comments.


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Comment at: llvm/trunk/lib/CodeGen/MachineCSE.cpp:814
+        unsigned NewReg = MRI->cloneVirtualRegister(VReg);
+        if (!isProfitableToCSE(NewReg, VReg, CMBB, MI))
+          continue;
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LuoYuanke wrote:
> Do we need to enhance the algorithm to consider more about register pressure on the profit calculation? I'm afraid there is performance drop when the register pressure is heavy.
Hi @LuoYuanke, yes, this could be the case. Actually this commit doesn't change profit calculation, `ProcessBlockPRE()` uses the same `isProfitableToCommit()` function as `ProcessBlockCSE()` uses. Do you have concrete test cases where register pressure increases?


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  rL LLVM

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  https://reviews.llvm.org/D56772/new/

https://reviews.llvm.org/D56772