[llvm] r364038 - [X86] X86ISD::ANDNP is a (non-commutative) binop

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Jun 21 05:42:39 2019
New Revision: 364038

URL: http://llvm.org/viewvc/llvm-project?rev=364038&view=rev
Log:
[X86] X86ISD::ANDNP is a (non-commutative) binop

The sat add/sub tests still have unnecessary extract_subvector((vandnps ymm, ymm), 0) uses that should be split to (vandnps (extract_subvector(ymm, 0), extract_subvector(ymm, 0)), but its getting better.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/vec_saddo.ll
    llvm/trunk/test/CodeGen/X86/vec_ssubo.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364038&r1=364037&r2=364038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 21 05:42:39 2019
@@ -28545,6 +28545,8 @@ bool X86TargetLowering::isVectorShiftByS
 
 bool X86TargetLowering::isBinOp(unsigned Opcode) const {
   switch (Opcode) {
+  // TODO: Add more X86ISD opcodes once we have test coverage.
+  case X86ISD::ANDNP:
   case X86ISD::PMULUDQ:
   case X86ISD::FMAX:
   case X86ISD::FMIN:

Modified: llvm/trunk/test/CodeGen/X86/vec_saddo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_saddo.ll?rev=364038&r1=364037&r2=364038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_saddo.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_saddo.ll Fri Jun 21 05:42:39 2019
@@ -814,7 +814,7 @@ define <16 x i32> @saddo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpgtd %xmm1, %xmm5, %xmm4
 ; AVX1-NEXT:    vpxor %xmm6, %xmm4, %xmm4
 ; AVX1-NEXT:    vpcmpeqd %xmm11, %xmm4, %xmm11
-; AVX1-NEXT:    vinsertf128 $1, %xmm8, %ymm11, %ymm8
+; AVX1-NEXT:    vinsertf128 $1, %xmm8, %ymm11, %ymm11
 ; AVX1-NEXT:    vpaddd %xmm9, %xmm7, %xmm9
 ; AVX1-NEXT:    vpcmpgtd %xmm9, %xmm5, %xmm7
 ; AVX1-NEXT:    vpxor %xmm6, %xmm7, %xmm7
@@ -824,8 +824,8 @@ define <16 x i32> @saddo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpxor %xmm6, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm4, %xmm1
 ; AVX1-NEXT:    vinsertf128 $1, %xmm7, %ymm1, %ymm1
-; AVX1-NEXT:    vandnps %ymm8, %ymm1, %ymm1
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT:    vandnps %ymm11, %ymm1, %ymm1
+; AVX1-NEXT:    vpandn %xmm8, %xmm7, %xmm4
 ; AVX1-NEXT:    vpackssdw %xmm4, %xmm1, %xmm8
 ; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm4
 ; AVX1-NEXT:    vpcmpgtd %xmm4, %xmm5, %xmm7
@@ -839,7 +839,7 @@ define <16 x i32> @saddo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpgtd %xmm0, %xmm5, %xmm7
 ; AVX1-NEXT:    vpxor %xmm6, %xmm7, %xmm7
 ; AVX1-NEXT:    vpcmpeqd %xmm12, %xmm7, %xmm12
-; AVX1-NEXT:    vinsertf128 $1, %xmm11, %ymm12, %ymm11
+; AVX1-NEXT:    vinsertf128 $1, %xmm11, %ymm12, %ymm12
 ; AVX1-NEXT:    vpaddd %xmm4, %xmm1, %xmm4
 ; AVX1-NEXT:    vpcmpgtd %xmm4, %xmm5, %xmm1
 ; AVX1-NEXT:    vpxor %xmm6, %xmm1, %xmm1
@@ -849,8 +849,8 @@ define <16 x i32> @saddo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpxor %xmm6, %xmm0, %xmm0
 ; AVX1-NEXT:    vpcmpeqd %xmm0, %xmm7, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT:    vandnps %ymm11, %ymm0, %ymm0
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vandnps %ymm12, %ymm0, %ymm0
+; AVX1-NEXT:    vpandn %xmm11, %xmm1, %xmm1
 ; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpacksswb %xmm8, %xmm0, %xmm1
 ; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm0

Modified: llvm/trunk/test/CodeGen/X86/vec_ssubo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ssubo.ll?rev=364038&r1=364037&r2=364038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_ssubo.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_ssubo.ll Fri Jun 21 05:42:39 2019
@@ -840,7 +840,7 @@ define <16 x i32> @ssubo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpgtd %xmm1, %xmm6, %xmm4
 ; AVX1-NEXT:    vpxor %xmm5, %xmm4, %xmm4
 ; AVX1-NEXT:    vpcmpeqd %xmm11, %xmm4, %xmm11
-; AVX1-NEXT:    vinsertf128 $1, %xmm8, %ymm11, %ymm8
+; AVX1-NEXT:    vinsertf128 $1, %xmm8, %ymm11, %ymm11
 ; AVX1-NEXT:    vpsubd %xmm9, %xmm7, %xmm9
 ; AVX1-NEXT:    vpcmpgtd %xmm9, %xmm6, %xmm7
 ; AVX1-NEXT:    vpxor %xmm5, %xmm7, %xmm7
@@ -852,8 +852,8 @@ define <16 x i32> @ssubo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm4, %xmm1
 ; AVX1-NEXT:    vpxor %xmm5, %xmm1, %xmm1
 ; AVX1-NEXT:    vinsertf128 $1, %xmm7, %ymm1, %ymm1
-; AVX1-NEXT:    vandnps %ymm1, %ymm8, %ymm1
-; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm4
+; AVX1-NEXT:    vandnps %ymm1, %ymm11, %ymm1
+; AVX1-NEXT:    vpandn %xmm7, %xmm8, %xmm4
 ; AVX1-NEXT:    vpackssdw %xmm4, %xmm1, %xmm8
 ; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm4
 ; AVX1-NEXT:    vpcmpgtd %xmm4, %xmm6, %xmm7
@@ -867,7 +867,7 @@ define <16 x i32> @ssubo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpgtd %xmm0, %xmm6, %xmm7
 ; AVX1-NEXT:    vpxor %xmm5, %xmm7, %xmm7
 ; AVX1-NEXT:    vpcmpeqd %xmm12, %xmm7, %xmm12
-; AVX1-NEXT:    vinsertf128 $1, %xmm11, %ymm12, %ymm11
+; AVX1-NEXT:    vinsertf128 $1, %xmm11, %ymm12, %ymm12
 ; AVX1-NEXT:    vpsubd %xmm4, %xmm1, %xmm4
 ; AVX1-NEXT:    vpcmpgtd %xmm4, %xmm6, %xmm1
 ; AVX1-NEXT:    vpxor %xmm5, %xmm1, %xmm1
@@ -879,8 +879,8 @@ define <16 x i32> @ssubo_v16i32(<16 x i3
 ; AVX1-NEXT:    vpcmpeqd %xmm0, %xmm7, %xmm0
 ; AVX1-NEXT:    vpxor %xmm5, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT:    vandnps %ymm0, %ymm11, %ymm0
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vandnps %ymm0, %ymm12, %ymm0
+; AVX1-NEXT:    vpandn %xmm1, %xmm11, %xmm1
 ; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpacksswb %xmm8, %xmm0, %xmm1
 ; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm0