[llvm] r364026 - [X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 21 04:13:15 PDT 2019
Author: rksimon
Date: Fri Jun 21 04:13:15 2019
New Revision: 364026
URL: http://llvm.org/viewvc/llvm-project?rev=364026&view=rev
Log:
[X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=364026&r1=364025&r2=364026&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 21 04:13:15 2019
@@ -41023,11 +41023,9 @@ static SDValue combineAndnp(SDNode *N, S
return DAG.getConstant(0, SDLoc(N), VT);
// Turn ANDNP back to AND if input is inverted.
- if (VT.isVector() && N->getOperand(0).getOpcode() == ISD::XOR &&
- ISD::isBuildVectorAllOnes(N->getOperand(0).getOperand(1).getNode())) {
- return DAG.getNode(ISD::AND, SDLoc(N), VT,
- N->getOperand(0).getOperand(0), N->getOperand(1));
- }
+ if (SDValue Not = IsNOT(N->getOperand(0), DAG))
+ return DAG.getNode(ISD::AND, SDLoc(N), VT, DAG.getBitcast(VT, Not),
+ N->getOperand(1));
// Attempt to recursively combine a bitmask ANDNP with shuffles.
if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
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