[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Ryan Taylor via Phabricator via llvm-commits]

rtaylor added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.td:2316
+  let FilterClass = "Base_SOPP";
+  let RowFields = ["AsmString"];
+  let ColFields = ["Size"];
----------------
rampitec wrote:
> I must be missing something, but how does it work? You are passing the same asm string into the both versions. What do you map to what then?
The asm string is the same for both, the s_nop is added in at encoding. I'm using the Size field, 4 maps to 8.

This is quite similar to how VOP is doing in during getVOPe32 and get VOPe64, the difference is that they also use a VOP3 flag but it's not needed here. Here, if you notice I am just adding the s_nop in class SOPP64e.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494