[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: lib/Target/AMDGPU/SIInstrInfo.td:2316
+  let FilterClass = "Base_SOPP";
+  let RowFields = ["AsmString"];
+  let ColFields = ["Size"];
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I must be missing something, but how does it work? You are passing the same asm string into the both versions. What do you map to what then?


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Comment at: test/MC/AMDGPU/offsetbug_once.s:9
+	s_nop 0
+        s_nop 0
+	s_nop 0
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Indent.


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Comment at: test/MC/AMDGPU/offsetbug_one_and_one.s:78
+	s_nop 0
+        s_endpgm
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Indent.


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Comment at: test/MC/AMDGPU/offsetbug_twice.s:112
+// BIN: s_cbranch_vccnz BB0_2 // 00000000017C: BF870003
+        s_nop 0
+        s_nop 0
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And indent ;)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494