[llvm] r363931 - Virtualize TargetInstrInfo::getRegClass()

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Thu Jun 20 07:59:28 2019
New Revision: 363931

URL: http://llvm.org/viewvc/llvm-project?rev=363931&view=rev
Log:
Virtualize TargetInstrInfo::getRegClass()

AMDGPU target needs to override getRegClass() used during
instruction selection. We now may have either 32 or 64 bit
conditional registers used in the same instructions. For
that purpose special SReg_1 register class is created which
is dynamically resolved to either SReg_64 or SGPR_32 depending
on the subtarget attributes.

Differential Revision: https://reviews.llvm.org/D63205

Modified:
    llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h

Modified: llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h?rev=363931&r1=363930&r2=363931&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetInstrInfo.h Thu Jun 20 07:59:28 2019
@@ -81,6 +81,7 @@ public:
 
   /// Given a machine instruction descriptor, returns the register
   /// class constraint for OpNum, or NULL.
+  virtual
   const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
                                          const TargetRegisterInfo *TRI,
                                          const MachineFunction &MF) const;