[PATCH] D63590: [PowerPC] Sign extend the select instr operands if it is any_extend

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: hfinkel, nemanjai, jsji.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: LLVM.

Though we have the patch https://reviews.llvm.org/D63318 to fold the aext + select in DAGCombine, PowerPC still have own combine rule to do this. However, it didn't handle the any extend well. For now, we will do the zero extend if the select operands are constant and it is fed by any_extend.

      t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
      t2: i64 = any_extend t1
  -->
   t3: i64 = select t0, Constant:i64<255>, Constant:i64<0>

The zero extend break the special pattern of "-1" and it might hurt some performance opportunity if they are caring about the sign bit.

This is what we want to do:

  -->
  t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
  -->
  t4: i64 = sign_extend_inreg t3


https://reviews.llvm.org/D63590

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/bool-math.ll
  llvm/test/CodeGen/PowerPC/select_const.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63590.205752.patch
Type: text/x-patch
Size: 13178 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190620/a3e85880/attachment.bin>