[PATCH] D63318: [DAGCombine] Teach DAGCombine to fold the aext + select pattern

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang marked an inline comment as done.
steven.zhang added a comment.

As the X86 review is done (Another issue exposed by this patch, and x86 backend will work on that ?), let's continue the review for the PowerPC backend and DAGCombine logic.



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Comment at: llvm/test/CodeGen/X86/cmov-promotion.ll:59
 ; CMOV-NEXT:    movl $255, %eax
-; CMOV-NEXT:    cmovnel %ecx, %eax
+; CMOV-NEXT:    cmovneq %rcx, %rax
 ; CMOV-NEXT:    retq
----------------
spatel wrote:
> steven.zhang wrote:
> > craig.topper wrote:
> > > The zextisfree check isn't enough to fix this :( It's an i8->i64 zext which isn't free. I guess we'll have to handle this in the x86 backend.
> > Yes. The hook only check the type i32->i64. Do we need to pass the value instead of the type for the isZextFree to fix this issue ?
> I don't think changing the TLI call will be enough to solve the general problem (the IR is likely already in the form that we're trying to avoid).
ok. That sounds to be another issue. 


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