[llvm] r363886 - [mips] Mark the `lwupc` instruction as MIPS64 R6 only
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 19 15:08:07 PDT 2019
Author: atanasyan
Date: Wed Jun 19 15:08:06 2019
New Revision: 363886
URL: http://llvm.org/viewvc/llvm-project?rev=363886&view=rev
Log:
[mips] Mark the `lwupc` instruction as MIPS64 R6 only
The "The MIPS64 Instruction Set Reference Manual" [1] states that
the `lwupc` is MIPS64 Release 6 only. It should not be supported
for 32-bit CPUs.
[1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
Modified:
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips32r6/relocations.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jun 19 15:08:06 2019
@@ -149,7 +149,6 @@ class SELEQZ_ENC : SPECIAL_3R_FM<0b00000
class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
-class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
@@ -325,7 +324,6 @@ class PCREL_DESC_BASE<string instr_asm,
class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
II_ADDIUPC>;
class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
-class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
Operand ImmOpnd, InstrItinClass itin>
@@ -926,7 +924,6 @@ let AdditionalPredicates = [NotInMicroMi
}
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
- def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jun 19 15:08:06 2019
@@ -36,6 +36,7 @@ class DMUHU_ENC : SPECIAL_3R_FM<0b0001
class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
+class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>;
@@ -72,6 +73,7 @@ class DMUHU_DESC : MUL_R6_DESC_BASE<"d
class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
+class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>;
class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
@@ -147,6 +149,7 @@ let AdditionalPredicates = [NotInMicroMi
def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
}
def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
+def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS64R6;
def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
let DecoderNamespace = "Mips32r6_64r6_GP64" in {
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt Wed Jun 19 15:08:06 2019
@@ -100,7 +100,6 @@
0x04 0x00 0x60 0x41 # CHECK: evp $zero
0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
-0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt Wed Jun 19 15:08:06 2019
@@ -192,7 +192,6 @@
0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
-0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32r2.s?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32r2.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips32r2.s Wed Jun 19 15:08:06 2019
@@ -5,6 +5,7 @@
# RUN: FileCheck %s < %t1
.set noat
+ lwupc $2,268 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r6/relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/relocations.s?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/relocations.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/relocations.s Wed Jun 19 15:08:06 2019
@@ -40,9 +40,6 @@
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
-# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
-# CHECK-FIXUP: # fixup A - offset: 0,
-# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
@@ -58,7 +55,6 @@
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
-# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ]
addiupc $2,bar
@@ -72,4 +68,3 @@
addiu $2, $2, %pcrel_lo(bar)
lapc $2,bar
lwpc $2,bar
- lwupc $2,bar
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=363886&r1=363885&r2=363886&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Wed Jun 19 15:08:06 2019
@@ -126,7 +126,6 @@ a:
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
- lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
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