[PATCH] D63568: hwasan: Shrink outlined checks by 1 instruction.

[Peter Collingbourne via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL363874: hwasan: Shrink outlined checks by 1 instruction. (authored by pcc, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D63568?vs=205657&id=205662#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63568/new/

https://reviews.llvm.org/D63568

Files:
  llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/trunk/test/CodeGen/AArch64/hwasan-check-memaccess.ll


Index: llvm/trunk/test/CodeGen/AArch64/hwasan-check-memaccess.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/hwasan-check-memaccess.ll
+++ llvm/trunk/test/CodeGen/AArch64/hwasan-check-memaccess.ll
@@ -38,8 +38,7 @@
 ; CHECK-NEXT: __hwasan_check_x0_456:
 ; CHECK-NEXT: ubfx x16, x0, #4, #52
 ; CHECK-NEXT: ldrb w16, [x9, x16]
-; CHECK-NEXT: lsr x17, x0, #56
-; CHECK-NEXT: cmp w16, w17
+; CHECK-NEXT: cmp x16, x0, lsr #56
 ; CHECK-NEXT: b.ne .Ltmp0
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: .Ltmp0:
@@ -58,8 +57,7 @@
 ; CHECK-NEXT: __hwasan_check_x1_123:
 ; CHECK-NEXT: ubfx x16, x1, #4, #52
 ; CHECK-NEXT: ldrb w16, [x9, x16]
-; CHECK-NEXT: lsr x17, x1, #56
-; CHECK-NEXT: cmp w16, w17
+; CHECK-NEXT: cmp x16, x1, lsr #56
 ; CHECK-NEXT: b.ne .Ltmp1
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: .Ltmp1:
Index: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -297,18 +297,13 @@
                                      .addImm(0)
                                      .addImm(0),
                                  *STI);
-    OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri)
-                                     .addReg(AArch64::X17)
-                                     .addReg(Reg)
-                                     .addImm(56)
-                                     .addImm(63),
-                                 *STI);
-    OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
-                                     .addReg(AArch64::WZR)
-                                     .addReg(AArch64::W16)
-                                     .addReg(AArch64::W17)
-                                     .addImm(0),
-                                 *STI);
+    OutStreamer->EmitInstruction(
+        MCInstBuilder(AArch64::SUBSXrs)
+            .addReg(AArch64::XZR)
+            .addReg(AArch64::X16)
+            .addReg(Reg)
+            .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
+        *STI);
     MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
     OutStreamer->EmitInstruction(
         MCInstBuilder(AArch64::Bcc)


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