[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Ryan Taylor via Phabricator via llvm-commits]

rtaylor marked an inline comment as done.
rtaylor added inline comments.


================
Comment at: lib/Target/AMDGPU/SOPInstructions.td:1011-1018
+def S_CBRANCH_SCC0_64 : SOPP64 <
+  0x00000004, (ins sopp_brtarget:$simm16),
+  "s_cbranch_scc0 $simm16"
+>;
+def S_CBRANCH_SCC1_64 : SOPP64 <
+  0x00000005, (ins sopp_brtarget:$simm16),
+  "s_cbranch_scc1 $simm16"
----------------
rtaylor wrote:
> arsenm wrote:
> > If the opcodes end up unavoidable, the class should be fixed to generate the branch and the dummy at the same time, rather than requiring repeating each definition with the opcode value
> I can have a look at doing this.
I don't think _Real is the best naming since there isn't a corresponding Pseudo but I had no clue what to call this multiclass so if anyone has a suggestion, I'm all ears.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494