[PATCH] D63517: [x86] avoid vector load narrowing with extracted store uses (PR42305)

[Sanjay Patel via Phabricator via llvm-commits]

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Comment at: llvm/test/CodeGen/X86/sandybridge-loads.ll:44
   ret void
 }
 
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RKSimon wrote:
> Not (very) related - but do we need a variant of this with that has an unaligned load:
> ```
>   %v0 = load <8 x float>, <8 x float>* %a, align 32 ; <--- aligned
>   %v1 = load <8 x float>, <8 x float>* %b, align 16 ; <--- unaligned
>   store <8 x float> %v0, <8 x float>* %b, align 32 ; <--- aligned
>   store <8 x float> %v1, <8 x float>* %a, align 16 ; <--- unaligned
>   ret void
> ```
I think for the purpose of this patch, that's covered by the next test diff (in widen_load-3.ll). 

And for the purpose of SandyBridge-specific (actual CPU feature is -slow-unaligned-mem-32), the test just above here covers it. But I can add that suggestion for completeness.


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