[PATCH] D62673: [ARM] Add MVE vector bit-operations (register inputs).

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham updated this revision to Diff 205615.
simon_tatham added a comment.

Addressed minor review comments (`isVectorIndex` family, pointless
suffixes on `size{1-0}` and similar). Also, fixed the incomprehensible
mess of MVE vector indices by rewriting the `MVE_VMOV_lane` class
hierarchy completely: by splitting it up in the other order (first by
lane size, then by transfer direction) I managed to arrange that the
lane index operand becomes a perfectly normal integer which doesn't
even need custom encode/decode methods at all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62673/new/

https://reviews.llvm.org/D62673

Files:
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/test/MC/ARM/mve-bitops.s
  llvm/test/MC/ARM/mve-vmov-lane.s
  llvm/test/MC/Disassembler/ARM/mve-bitops.txt
  llvm/test/MC/Disassembler/ARM/mve-vmov-lane.txt

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