[PATCH] D62341: [DAGCombine][X86][AArch64][AMDGPU][MIPS][PPC] (sub x, c) -> (add x, -c) vector edition.
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 19 06:02:12 PDT 2019
arsenm added inline comments.
================
Comment at: test/CodeGen/AMDGPU/sub.v2i16.ll:329
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32
+; GFX9-NEXT: v_pk_add_u16 v0, v0, s8
; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
----------------
arsenm wrote:
> This is worse because it is no longer an inline immediate. We undo this already for the 32-bit case during selection:
>
>
> // Undo sub x, c -> add x, -c canonicalization since c is more likely
> // an inline immediate than -c.
> // TODO: Also do for 64-bit.
> def : GCNPat<
> (add i32:$src0, (i32 NegSubInlineConst32:$src1)),
> (S_SUB_I32 $src0, NegSubInlineConst32:$src1)
> >;
>
I have a patch which should implement this for the v2i16 case
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62341/new/
https://reviews.llvm.org/D62341
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