[llvm] r363787 - [DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Jun 19 04:17:48 2019
New Revision: 363787

URL: http://llvm.org/viewvc/llvm-project?rev=363787&view=rev
Log:
[DAGCombine] Fix (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2)) comment. NFCI.

We pre-extend, not post.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/combine-shl.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=363787&r1=363786&r2=363787&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jun 19 04:17:48 2019
@@ -7167,6 +7167,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
   if (DAG.MaskedValueIsZero(SDValue(N, 0),
                             APInt::getAllOnesValue(OpSizeInBits)))
     return DAG.getConstant(0, SDLoc(N), VT);
+
   // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND) {
@@ -7204,7 +7205,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
     }
   }
 
-  // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
+  // fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))
   // For this to be valid, the second form must not preserve any of the bits
   // that are shifted out by the inner shift in the first form.  This means
   // the outer shift size must be >= the number of bits added by the ext.

Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=363787&r1=363786&r2=363787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Wed Jun 19 04:17:48 2019
@@ -233,7 +233,7 @@ define <4 x i32> @combine_vec_shl_shl_ze
   ret <4 x i32> %2
 }
 
-; fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
+; fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))
 define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {
 ; SSE2-LABEL: combine_vec_shl_ext_shl0:
 ; SSE2:       # %bb.0: