[PATCH] D63520: correct SILowerI1Copies for vgprs

Tue Jun 18 16:35:55 PDT 2019

arsenm added inline comments.

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Comment at: lib/Target/AMDGPU/SILowerI1Copies.cpp:691-693
+      if (AMDGPU::VGPR_32RegClass.contains(SrcReg) &&  
+           (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
+              !isLaneMaskReg(SrcReg))) {
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I don't see where the physical register check is coming from. If SrcReg is a virtual register (which it should be), this should crash?

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Comment at: test/CodeGen/AMDGPU/si-lower-i1-copies-vgpr.mir:2
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s
+# GCN-LABEL: name: inserted_cmp_operand_class
+---
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This isn't really checking anything. Generated checks with update_mir_test_checks are probably OK

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63520/new/

https://reviews.llvm.org/D63520