[PATCH] D63506: [AMDGPU] gfx1010 disassembler changes for wave32
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 18 11:29:59 PDT 2019
rampitec created this revision.
rampitec added reviewers: kzhuravl, msearles.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, arsenm.
Yet another independent part of D63204 <https://reviews.llvm.org/D63204>.
https://reviews.llvm.org/D63506
Files:
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
Index: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
===================================================================
--- lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -123,6 +123,8 @@
MCOperand decodeSDWASrc32(unsigned Val) const;
MCOperand decodeSDWAVopcDst(unsigned Val) const;
+ MCOperand decodeBoolReg(unsigned Val) const;
+
int getTTmpIdx(unsigned Val) const;
bool isVI() const;
Index: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
===================================================================
--- lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1039,6 +1039,8 @@
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
"SDWAVopcDst should be present only on GFX9+");
+ bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
+
if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
@@ -1046,15 +1048,21 @@
if (TTmpIdx >= 0) {
return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
} else if (Val > SGPR_MAX) {
- return decodeSpecialReg64(Val);
+ return IsWave64 ? decodeSpecialReg64(Val)
+ : decodeSpecialReg32(Val);
} else {
- return createSRegOperand(getSgprClassId(OPW64), Val);
+ return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
}
} else {
- return createRegOperand(AMDGPU::VCC);
+ return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
}
}
+MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
+ return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
+ decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
+}
+
bool AMDGPUDisassembler::isVI() const {
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
}
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