[PATCH] D62857: [RISCV] Prevent re-ordering some adds after shifts

[Sam Elliott via Phabricator via llvm-commits]

lenary updated this revision to Diff 205350.
lenary added a comment.

Address review feedback

- Update `getIntMatCost` to take an integer size (in bits). This ensures we chunk the constant correctly for the legal types on the target, and account for the costs of all required chunks. I was unable to devise a simple test case for when this behaviour would not match the behaivour using `getMinSignedBits`, due to legalisation always splitting the wider type before the `isDesirableToCommuteWithShift` callback is called.

  The chunking will automatically expand each chunk to be the platform register width, so we don't need to sign extend the constant to be a multiple of that width before we start chunking.

- Update and de-duplicate comments on tests and implementations
- Update naming of `IsRV64` parameter in RISCVMatInt.{h,cpp}


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62857/new/

https://reviews.llvm.org/D62857

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
  llvm/lib/Target/RISCV/Utils/RISCVMatInt.h
  llvm/test/CodeGen/RISCV/add-before-shl.ll

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