[PATCH] D63455: [AMDGPU] Propagate function attributes thru bitcasts

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL363614: [AMDGPU] Propagate function attributes thru bitcasts (authored by rampitec, committed by ).
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D63455?vs=205167&id=205170#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63455/new/

https://reviews.llvm.org/D63455

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/trunk/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll


Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -658,14 +658,15 @@
   disablePass(&FuncletLayoutID);
   disablePass(&PatchableFunctionID);
 
+  // This must occur before inlining, as the inliner will not look through
+  // bitcast calls.
+  addPass(createAMDGPUFixFunctionBitcastsPass());
+
   // A call to propagate attributes pass in the backend in case opt was not run.
   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
 
   addPass(createAtomicExpandPass());
 
-  // This must occur before inlining, as the inliner will not look through
-  // bitcast calls.
-  addPass(createAMDGPUFixFunctionBitcastsPass());
 
   addPass(createAMDGPULowerIntrinsicsPass());
 
Index: llvm/trunk/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN: foo1:
+; v_cndmask_b32_e64 v0, 0, 1, vcc_lo{{$}}
+; GCN: kernel1:
+; GCN: foo1 at gotpcrel32@lo+4
+; GCN: foo1 at gotpcrel32@hi+4
+
+define void @foo1(i32 %x) #1 {
+entry:
+  %cc = icmp eq i32 %x, 0
+  store volatile i1 %cc, i1* undef
+  ret void
+}
+
+define amdgpu_kernel void @kernel1(float %x) #0 {
+entry:
+  call void bitcast (void (i32)* @foo1 to void (float)*)(float %x)
+  ret void
+}
+
+attributes #0 = { nounwind "target-features"="+wavefrontsize32" }
+attributes #1 = { noinline nounwind "target-features"="+wavefrontsize64" }


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