[llvm] r363643 - [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 17 20:23:12 PDT 2019
Author: ctopper
Date: Mon Jun 17 20:23:11 2019
New Revision: 363643
URL: http://llvm.org/viewvc/llvm-project?rev=363643&view=rev
Log:
[X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.
Rename the old versions that use FR32/FR64 to MOVSSrm_alt/MOVSDrm_alt.
Use the new versions in patterns that previously used a COPY_TO_REGCLASS
to VR128. These patterns expect the upper bits to be zero. The
current set up appears to work, but I'm not sure we should be
enforcing upper bits being zero through a COPY_TO_REGCLASS.
I wanted to flip the arrangement and use a COPY_TO_REGCLASS to
FR32/FR64 for the patterns that need an f32/f64 result, but that
complicated fastisel and globalisel.
I've been doing some experiments with reducing some isel patterns
and ended up in a situation where I had a
(SUBREG_TO_REG (COPY_TO_RECLASS (VMOVSSrm), VR128)) and our
post-isel peephole was unable to avoid using an instruction for
the SUBREG_TO_REG due to the COPY_TO_REGCLASS. Having a VR128
instruction removes the COPY_TO_REGCLASS that was breaking this.
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
llvm/trunk/test/CodeGen/X86/fast-isel-fneg-kill.ll
llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir
llvm/trunk/test/CodeGen/X86/pr30821.mir
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstComments.cpp?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86InstComments.cpp Mon Jun 17 20:23:11 2019
@@ -1075,9 +1075,12 @@ bool llvm::EmitAnyX86InstComments(const
Src1Name = getRegName(MI->getOperand(1).getReg());
LLVM_FALLTHROUGH;
+ case X86::MOVSDrm_alt:
case X86::MOVSDrm:
+ case X86::VMOVSDrm_alt:
case X86::VMOVSDrm:
case X86::VMOVSDZrm:
+ case X86::VMOVSDZrm_alt:
DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
@@ -1090,8 +1093,11 @@ bool llvm::EmitAnyX86InstComments(const
LLVM_FALLTHROUGH;
case X86::MOVSSrm:
+ case X86::MOVSSrm_alt:
case X86::VMOVSSrm:
+ case X86::VMOVSSrm_alt:
case X86::VMOVSSZrm:
+ case X86::VMOVSSZrm_alt:
DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Jun 17 20:23:11 2019
@@ -347,13 +347,17 @@ bool X86FastISel::X86FastEmitLoad(MVT VT
break;
case MVT::f32:
if (X86ScalarSSEf32)
- Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
+ Opc = HasAVX512 ? X86::VMOVSSZrm_alt :
+ HasAVX ? X86::VMOVSSrm_alt :
+ X86::MOVSSrm_alt;
else
Opc = X86::LD_Fp32m;
break;
case MVT::f64:
if (X86ScalarSSEf64)
- Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm;
+ Opc = HasAVX512 ? X86::VMOVSDZrm_alt :
+ HasAVX ? X86::VMOVSDrm_alt :
+ X86::MOVSDrm_alt;
else
Opc = X86::LD_Fp64m;
break;
@@ -3575,7 +3579,7 @@ bool X86FastISel::fastLowerCall(CallLowe
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc)), FI)
.addReg(CopyReg);
- Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
+ Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt;
addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg + i), FI);
}
@@ -3743,13 +3747,17 @@ unsigned X86FastISel::X86MaterializeFP(c
default: return 0;
case MVT::f32:
if (X86ScalarSSEf32)
- Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
+ Opc = HasAVX512 ? X86::VMOVSSZrm_alt :
+ HasAVX ? X86::VMOVSSrm_alt :
+ X86::MOVSSrm_alt;
else
Opc = X86::LD_Fp32m;
break;
case MVT::f64:
if (X86ScalarSSEf64)
- Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm;
+ Opc = HasAVX512 ? X86::VMOVSDZrm_alt :
+ HasAVX ? X86::VMOVSDrm_alt :
+ X86::MOVSDrm_alt;
else
Opc = X86::LD_Fp64m;
break;
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Jun 17 20:23:11 2019
@@ -3917,11 +3917,18 @@ multiclass avx512_move_scalar<string asm
(_.VT (OpNode _.RC:$src1, _.RC:$src2)),
(_.VT _.RC:$src0))))],
_.ExeDomain>, EVEX_4V, EVEX_K, Sched<[SchedWriteFShuffle.XMM]>;
- let canFoldAsLoad = 1, isReMaterializable = 1 in
- def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
+ let canFoldAsLoad = 1, isReMaterializable = 1 in {
+ def rm : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst), (ins _.ScalarMemOp:$src),
!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
- [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
+ [(set _.RC:$dst, (_.VT (X86vzload addr:$src)))],
_.ExeDomain>, EVEX, Sched<[WriteFLoad]>;
+ // _alt version uses FR32/FR64 register class.
+ let isCodeGenOnly = 1 in
+ def rm_alt : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
+ !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
+ [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
+ _.ExeDomain>, EVEX, Sched<[WriteFLoad]>;
+ }
let mayLoad = 1, hasSideEffects = 0 in {
let Constraints = "$src0 = $dst" in
def rmk : AVX512PI<0x10, MRMSrcMem, (outs _.RC:$dst),
@@ -4359,20 +4366,16 @@ let Predicates = [HasAVX512] in {
// MOVSSrm zeros the high parts of the register; represent this
// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
- (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
+ (VMOVSSZrm addr:$src)>;
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
- (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
- def : Pat<(v4f32 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
+ (VMOVSSZrm addr:$src)>;
// MOVSDrm zeros the high parts of the register; represent this
// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
- (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
+ (VMOVSDZrm addr:$src)>;
def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
- (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
- def : Pat<(v2f64 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
+ (VMOVSDZrm addr:$src)>;
// Represent the same patterns above but in the form they appear for
// 256-bit types
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Mon Jun 17 20:23:11 2019
@@ -1105,18 +1105,18 @@ def : Pat<(atomic_store_64 addr:$dst, (i
(VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>;
def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
- (MOVSSrm addr:$src)>, Requires<[UseSSE1]>;
+ (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>;
def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
- (VMOVSSrm addr:$src)>, Requires<[UseAVX]>;
+ (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>;
def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
- (VMOVSSZrm addr:$src)>, Requires<[HasAVX512]>;
+ (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>;
def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
- (MOVSDrm addr:$src)>, Requires<[UseSSE2]>;
+ (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>;
def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
- (VMOVSDrm addr:$src)>, Requires<[UseAVX]>;
+ (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>;
def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
- (VMOVSDZrm addr:$src)>, Requires<[HasAVX512]>;
+ (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>;
//===----------------------------------------------------------------------===//
// DAG Pattern Matching Rules
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jun 17 20:23:11 2019
@@ -219,16 +219,22 @@ static bool isFrameLoadOpcode(int Opcode
return true;
case X86::MOV32rm:
case X86::MOVSSrm:
- case X86::VMOVSSZrm:
+ case X86::MOVSSrm_alt:
case X86::VMOVSSrm:
+ case X86::VMOVSSrm_alt:
+ case X86::VMOVSSZrm:
+ case X86::VMOVSSZrm_alt:
case X86::KMOVDkm:
MemBytes = 4;
return true;
case X86::MOV64rm:
case X86::LD_Fp64m:
case X86::MOVSDrm:
+ case X86::MOVSDrm_alt:
case X86::VMOVSDrm:
+ case X86::VMOVSDrm_alt:
case X86::VMOVSDZrm:
+ case X86::VMOVSDZrm_alt:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
case X86::KMOVQkm:
@@ -483,7 +489,9 @@ bool X86InstrInfo::isReallyTriviallyReMa
case X86::MOV32rm:
case X86::MOV64rm:
case X86::MOVSSrm:
+ case X86::MOVSSrm_alt:
case X86::MOVSDrm:
+ case X86::MOVSDrm_alt:
case X86::MOVAPSrm:
case X86::MOVUPSrm:
case X86::MOVAPDrm:
@@ -491,7 +499,9 @@ bool X86InstrInfo::isReallyTriviallyReMa
case X86::MOVDQArm:
case X86::MOVDQUrm:
case X86::VMOVSSrm:
+ case X86::VMOVSSrm_alt:
case X86::VMOVSDrm:
+ case X86::VMOVSDrm_alt:
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
@@ -508,7 +518,9 @@ bool X86InstrInfo::isReallyTriviallyReMa
case X86::MMX_MOVQ64rm:
// AVX-512
case X86::VMOVSSZrm:
+ case X86::VMOVSSZrm_alt:
case X86::VMOVSDZrm:
+ case X86::VMOVSDZrm_alt:
case X86::VMOVAPDZ128rm:
case X86::VMOVAPDZ256rm:
case X86::VMOVAPDZrm:
@@ -2879,8 +2891,12 @@ static unsigned getLoadStoreRegOpcode(un
return load ? X86::MOV32rm : X86::MOV32mr;
if (X86::FR32XRegClass.hasSubClassEq(RC))
return load ?
- (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
- (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
+ (HasAVX512 ? X86::VMOVSSZrm_alt :
+ HasAVX ? X86::VMOVSSrm_alt :
+ X86::MOVSSrm_alt) :
+ (HasAVX512 ? X86::VMOVSSZmr :
+ HasAVX ? X86::VMOVSSmr :
+ X86::MOVSSmr);
if (X86::RFP32RegClass.hasSubClassEq(RC))
return load ? X86::LD_Fp32m : X86::ST_Fp32m;
if (X86::VK32RegClass.hasSubClassEq(RC)) {
@@ -2901,8 +2917,12 @@ static unsigned getLoadStoreRegOpcode(un
return load ? X86::MOV64rm : X86::MOV64mr;
if (X86::FR64XRegClass.hasSubClassEq(RC))
return load ?
- (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
- (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
+ (HasAVX512 ? X86::VMOVSDZrm_alt :
+ HasAVX ? X86::VMOVSDrm_alt :
+ X86::MOVSDrm_alt) :
+ (HasAVX512 ? X86::VMOVSDZmr :
+ HasAVX ? X86::VMOVSDmr :
+ X86::MOVSDmr);
if (X86::VR64RegClass.hasSubClassEq(RC))
return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
if (X86::RFP64RegClass.hasSubClassEq(RC))
@@ -4861,7 +4881,9 @@ static bool isNonFoldablePartialRegister
MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
unsigned RegSize = TRI.getRegSizeInBits(*RC);
- if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
+ if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
+ Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
+ Opc == X86::VMOVSSZrm_alt) &&
RegSize > 32) {
// These instructions only load 32 bits, we can't fold them if the
// destination register is wider than 32 bits (4 bytes), and its user
@@ -4913,7 +4935,9 @@ static bool isNonFoldablePartialRegister
}
}
- if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
+ if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
+ Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
+ Opc == X86::VMOVSDZrm_alt) &&
RegSize > 64) {
// These instructions only load 64 bits, we can't fold them if the
// destination register is wider than 64 bits (8 bytes), and its user
@@ -5452,7 +5476,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::LD_Fp64m:
case X86::LD_Fp80m:
case X86::MOVSSrm:
+ case X86::MOVSSrm_alt:
case X86::MOVSDrm:
+ case X86::MOVSDrm_alt:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
case X86::MOVAPSrm:
@@ -5463,7 +5489,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::MOVDQUrm:
// AVX load instructions
case X86::VMOVSSrm:
+ case X86::VMOVSSrm_alt:
case X86::VMOVSDrm:
+ case X86::VMOVSDrm_alt:
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
@@ -5478,7 +5506,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::VMOVDQUYrm:
// AVX512 load instructions
case X86::VMOVSSZrm:
+ case X86::VMOVSSZrm_alt:
case X86::VMOVSDZrm:
+ case X86::VMOVSDZrm_alt:
case X86::VMOVAPSZ128rm:
case X86::VMOVUPSZ128rm:
case X86::VMOVAPSZ128rm_NOVLX:
@@ -5529,7 +5559,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::LD_Fp64m:
case X86::LD_Fp80m:
case X86::MOVSSrm:
+ case X86::MOVSSrm_alt:
case X86::MOVSDrm:
+ case X86::MOVSDrm_alt:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
case X86::MOVAPSrm:
@@ -5540,7 +5572,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::MOVDQUrm:
// AVX load instructions
case X86::VMOVSSrm:
+ case X86::VMOVSSrm_alt:
case X86::VMOVSDrm:
+ case X86::VMOVSDrm_alt:
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
@@ -5555,7 +5589,9 @@ X86InstrInfo::areLoadsFromSameBasePtr(SD
case X86::VMOVDQUYrm:
// AVX512 load instructions
case X86::VMOVSSZrm:
+ case X86::VMOVSSZrm_alt:
case X86::VMOVSDZrm:
+ case X86::VMOVSDZrm_alt:
case X86::VMOVAPSZ128rm:
case X86::VMOVUPSZ128rm:
case X86::VMOVAPSZ128rm_NOVLX:
@@ -5727,7 +5763,9 @@ static const uint16_t ReplaceableInstrs[
{ X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
{ X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
{ X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
+ { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
{ X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
+ { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
{ X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
{ X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
{ X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
@@ -5757,7 +5795,9 @@ static const uint16_t ReplaceableInstrs[
{ X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
{ X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
{ X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
+ { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
{ X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
+ { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
{ X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
{ X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
{ X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
@@ -5796,7 +5836,9 @@ static const uint16_t ReplaceableInstrs[
{ X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
{ X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
{ X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
+ { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm },
{ X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
+ { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm },
{ X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
{ X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
{ X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jun 17 20:23:11 2019
@@ -225,16 +225,28 @@ multiclass sse12_move<RegisterClass RC,
}
// Loading from memory automatically zeroing upper bits.
-multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
+multiclass sse12_move_rm<RegisterClass RC, ValueType vt, X86MemOperand x86memop,
PatFrag mem_pat, string OpcodeStr, Domain d> {
- def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ def V#NAME#rm : SI<0x10, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set RC:$dst, (mem_pat addr:$src))], d>,
+ [(set VR128:$dst, (vt (X86vzload addr:$src)))], d>,
VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG;
- def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ def NAME#rm : SI<0x10, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set RC:$dst, (mem_pat addr:$src))], d>,
+ [(set VR128:$dst, (vt (X86vzload addr:$src)))], d>,
Sched<[WriteFLoad]>;
+
+ // _alt version uses FR32/FR64 register class.
+ let isCodeGenOnly = 1 in {
+ def V#NAME#rm_alt : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set RC:$dst, (mem_pat addr:$src))], d>,
+ VEX, VEX_LIG, Sched<[WriteFLoad]>, VEX_WIG;
+ def NAME#rm_alt : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set RC:$dst, (mem_pat addr:$src))], d>,
+ Sched<[WriteFLoad]>;
+ }
}
defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
@@ -243,9 +255,9 @@ defm MOVSD : sse12_move<FR64, X86Movsd,
SSEPackedDouble, "MOVSD", UseSSE2>, XD;
let canFoldAsLoad = 1, isReMaterializable = 1 in {
- defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
+ defm MOVSS : sse12_move_rm<FR32, v4f32, f32mem, loadf32, "movss",
SSEPackedSingle>, XS;
- defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
+ defm MOVSD : sse12_move_rm<FR64, v2f64, f64mem, loadf64, "movsd",
SSEPackedDouble>, XD;
}
@@ -254,20 +266,20 @@ let Predicates = [UseAVX] in {
// MOVSSrm zeros the high parts of the register; represent this
// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
- (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
+ (VMOVSSrm addr:$src)>;
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
- (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
+ (VMOVSSrm addr:$src)>;
def : Pat<(v4f32 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
+ (VMOVSSrm addr:$src)>;
// MOVSDrm zeros the high parts of the register; represent this
// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
- (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
+ (VMOVSDrm addr:$src)>;
def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
- (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
+ (VMOVSDrm addr:$src)>;
def : Pat<(v2f64 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
+ (VMOVSDrm addr:$src)>;
// Represent the same patterns above but in the form they appear for
// 256-bit types
@@ -325,21 +337,17 @@ let Predicates = [UseSSE1] in {
// MOVSSrm already zeros the high parts of the register.
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
- (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
+ (MOVSSrm addr:$src)>;
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
- (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
- def : Pat<(v4f32 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
+ (MOVSSrm addr:$src)>;
}
let Predicates = [UseSSE2] in {
// MOVSDrm already zeros the high parts of the register.
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
- (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
+ (MOVSDrm addr:$src)>;
def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
- (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
- def : Pat<(v2f64 (X86vzload addr:$src)),
- (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
+ (MOVSDrm addr:$src)>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Mon Jun 17 20:23:11 2019
@@ -418,18 +418,22 @@ unsigned X86InstructionSelector::getLoad
if (X86::GPRRegBankID == RB.getID())
return Isload ? X86::MOV32rm : X86::MOV32mr;
if (X86::VECRRegBankID == RB.getID())
- return Isload ? (HasAVX512 ? X86::VMOVSSZrm
- : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm)
- : (HasAVX512 ? X86::VMOVSSZmr
- : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
+ return Isload ? (HasAVX512 ? X86::VMOVSSZrm_alt :
+ HasAVX ? X86::VMOVSSrm_alt :
+ X86::MOVSSrm_alt)
+ : (HasAVX512 ? X86::VMOVSSZmr :
+ HasAVX ? X86::VMOVSSmr :
+ X86::MOVSSmr);
} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
if (X86::GPRRegBankID == RB.getID())
return Isload ? X86::MOV64rm : X86::MOV64mr;
if (X86::VECRRegBankID == RB.getID())
- return Isload ? (HasAVX512 ? X86::VMOVSDZrm
- : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm)
- : (HasAVX512 ? X86::VMOVSDZmr
- : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
+ return Isload ? (HasAVX512 ? X86::VMOVSDZrm_alt :
+ HasAVX ? X86::VMOVSDrm_alt :
+ X86::MOVSDrm_alt)
+ : (HasAVX512 ? X86::VMOVSDZmr :
+ HasAVX ? X86::VMOVSDmr :
+ X86::MOVSDmr);
} else if (Ty.isVector() && Ty.getSizeInBits() == 128) {
if (Alignment >= 16)
return Isload ? (HasVLX ? X86::VMOVAPSZ128rm
Modified: llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir Mon Jun 17 20:23:11 2019
@@ -465,11 +465,11 @@ body: |
bb.0.entry:
liveins: $rdi, $rsi
; CHECK-LABEL: name: aa_scope
- ; CHECK: $xmm0 = MOVSSrm $rsi, 1, $noreg, 0, $noreg :: (load 4 from %ir.c, !alias.scope !9)
- $xmm0 = MOVSSrm $rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
+ ; CHECK: $xmm0 = MOVSSrm_alt $rsi, 1, $noreg, 0, $noreg :: (load 4 from %ir.c, !alias.scope !9)
+ $xmm0 = MOVSSrm_alt $rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
; CHECK-NEXT: MOVSSmr $rdi, 1, $noreg, 20, $noreg, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
MOVSSmr $rdi, 1, _, 20, _, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
- $xmm0 = MOVSSrm killed $rsi, 1, _, 0, _ :: (load 4 from %ir.c)
+ $xmm0 = MOVSSrm_alt killed $rsi, 1, _, 0, _ :: (load 4 from %ir.c)
MOVSSmr killed $rdi, 1, _, 28, _, killed $xmm0 :: (store 4 into %ir.arrayidx)
RETQ
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir Mon Jun 17 20:23:11 2019
@@ -29,29 +29,29 @@ registers:
body: |
bb.1.entry:
; CHECK_NOPIC64-LABEL: name: test_float
- ; CHECK_NOPIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
+ ; CHECK_NOPIC64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
; CHECK_NOPIC64: $xmm0 = COPY [[COPY]]
; CHECK_NOPIC64: RET 0, implicit $xmm0
; CHECK_LARGE64-LABEL: name: test_float
; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
- ; CHECK_LARGE64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 32)
- ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
+ ; CHECK_LARGE64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 32)
+ ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
; CHECK_LARGE64: $xmm0 = COPY [[COPY]]
; CHECK_LARGE64: RET 0, implicit $xmm0
; CHECK_SMALL32-LABEL: name: test_float
- ; CHECK_SMALL32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
+ ; CHECK_SMALL32: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
; CHECK_SMALL32: $xmm0 = COPY [[COPY]]
; CHECK_SMALL32: RET 0, implicit $xmm0
; CHECK_LARGE32-LABEL: name: test_float
- ; CHECK_LARGE32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
+ ; CHECK_LARGE32: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
; CHECK_LARGE32: $xmm0 = COPY [[COPY]]
; CHECK_LARGE32: RET 0, implicit $xmm0
; CHECK_PIC64-LABEL: name: test_float
- ; CHECK_PIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]]
+ ; CHECK_PIC64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
; CHECK_PIC64: $xmm0 = COPY [[COPY]]
; CHECK_PIC64: RET 0, implicit $xmm0
%0:vecr(s32) = G_FCONSTANT float 5.500000e+00
@@ -76,29 +76,29 @@ registers:
body: |
bb.1.entry:
; CHECK_NOPIC64-LABEL: name: test_double
- ; CHECK_NOPIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
+ ; CHECK_NOPIC64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
; CHECK_NOPIC64: $xmm0 = COPY [[COPY]]
; CHECK_NOPIC64: RET 0, implicit $xmm0
; CHECK_LARGE64-LABEL: name: test_double
; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
- ; CHECK_LARGE64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 64)
- ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
+ ; CHECK_LARGE64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load 8 from constant-pool, align 64)
+ ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
; CHECK_LARGE64: $xmm0 = COPY [[COPY]]
; CHECK_LARGE64: RET 0, implicit $xmm0
; CHECK_SMALL32-LABEL: name: test_double
- ; CHECK_SMALL32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
+ ; CHECK_SMALL32: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
; CHECK_SMALL32: $xmm0 = COPY [[COPY]]
; CHECK_SMALL32: RET 0, implicit $xmm0
; CHECK_LARGE32-LABEL: name: test_double
- ; CHECK_LARGE32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
+ ; CHECK_LARGE32: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
; CHECK_LARGE32: $xmm0 = COPY [[COPY]]
; CHECK_LARGE32: RET 0, implicit $xmm0
; CHECK_PIC64-LABEL: name: test_double
- ; CHECK_PIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]]
+ ; CHECK_PIC64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
; CHECK_PIC64: $xmm0 = COPY [[COPY]]
; CHECK_PIC64: RET 0, implicit $xmm0
%0:vecr(s64) = G_FCONSTANT double 5.500000e+00
Modified: llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir (original)
+++ llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir Mon Jun 17 20:23:11 2019
@@ -2266,6 +2266,8 @@ body: |
VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
; CHECK: $xmm0 = VMOVSDrm $rip, 1, $noreg, 0, $noreg
$xmm0 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg
+ ; CHECK: $xmm0 = VMOVSDrm_alt $rip, 1, $noreg, 0, $noreg
+ $xmm0 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg
; CHECK: $xmm0 = VMOVSDrr $xmm0, $xmm1
$xmm0 = VMOVSDZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMOVSDrr_REV $xmm0, $xmm1
@@ -2278,6 +2280,8 @@ body: |
VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
; CHECK: $xmm0 = VMOVSSrm $rip, 1, $noreg, 0, $noreg
$xmm0 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg
+ ; CHECK: $xmm0 = VMOVSSrm_alt $rip, 1, $noreg, 0, $noreg
+ $xmm0 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg
; CHECK: $xmm0 = VMOVSSrr $xmm0, $xmm1
$xmm0 = VMOVSSZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMOVSSrr_REV $xmm0, $xmm1
@@ -4650,6 +4654,8 @@ body: |
VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
; CHECK: $xmm16 = VMOVSDZrm $rip, 1, $rax, 0, $noreg
$xmm16 = VMOVSDZrm $rip, 1, $rax, 0, $noreg
+ ; CHECK: $xmm16 = VMOVSDZrm_alt $rip, 1, $rax, 0, $noreg
+ $xmm16 = VMOVSDZrm_alt $rip, 1, $rax, 0, $noreg
; CHECK: $xmm16 = VMOVSDZrr $xmm16, $xmm1
$xmm16 = VMOVSDZrr $xmm16, $xmm1
; CHECK: $xmm16 = VMOVSDZrr_REV $xmm16, $xmm1
@@ -4662,6 +4668,8 @@ body: |
VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
; CHECK: $xmm16 = VMOVSSZrm $rip, 1, $rax, 0, $noreg
$xmm16 = VMOVSSZrm $rip, 1, $rax, 0, $noreg
+ ; CHECK: $xmm16 = VMOVSSZrm_alt $rip, 1, $rax, 0, $noreg
+ $xmm16 = VMOVSSZrm_alt $rip, 1, $rax, 0, $noreg
; CHECK: $xmm16 = VMOVSSZrr $xmm16, $xmm1
$xmm16 = VMOVSSZrr $xmm16, $xmm1
; CHECK: $xmm16 = VMOVSSZrr_REV $xmm16, $xmm1
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-fneg-kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-fneg-kill.ll?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-fneg-kill.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-fneg-kill.ll Mon Jun 17 20:23:11 2019
@@ -8,7 +8,7 @@ define void @goo(double* %x, double* %y)
; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi
; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]]
; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]]
-; CHECK-NEXT: %[[REG10:.*]]:fr64 = MOVSDrm %[[REG1]], 1, $noreg, 0, $noreg :: (load 8 from %ir.x)
+; CHECK-NEXT: %[[REG10:.*]]:fr64 = MOVSDrm_alt %[[REG1]], 1, $noreg, 0, $noreg :: (load 8 from %ir.x)
; CHECK-NEXT: %[[REG6:.*]]:gr64 = MOVSDto64rr killed %[[REG10]]
; CHECK-NEXT: %[[REG7:.*]]:gr64 = MOV64ri -9223372036854775808
; CHECK-NEXT: %[[REG8:.*]]:gr64 = XOR64rr killed %[[REG6]], %[[REG7]], implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir (original)
+++ llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir Mon Jun 17 20:23:11 2019
@@ -181,7 +181,7 @@ body: |
$xmm0 = XORPSrr undef $xmm0, undef $xmm0
$esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags
$rax = MOV64ri %const.0
- $xmm1 = MOVSDrm killed $rax, 1, $noreg, 0, $noreg :: (load 8 from constant-pool)
+ $xmm1 = MOVSDrm_alt killed $rax, 1, $noreg, 0, $noreg :: (load 8 from constant-pool)
MOVSDmr $rsp, 1, $noreg, 40, $noreg, killed $xmm1 :: (store 8 into %stack.4)
$eax = IMPLICIT_DEF
$ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
@@ -263,7 +263,7 @@ body: |
$eax = LEA64_32r $rbx, 1, $noreg, 1, _
$ecx = MOV32ri 6
CMP32ri $eax, 15141, implicit-def $eflags
- $xmm0 = MOVSDrm $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.4)
+ $xmm0 = MOVSDrm_alt $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.4)
JCC_1 %bb.4.bb7, 12, implicit $eflags
bb.11.bb51.loopexit:
@@ -273,7 +273,7 @@ body: |
$ebp = INC32r killed $ebp, implicit-def dead $eflags
$ebx = INC32r $ebx, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx
$rax = MOV64ri %const.0
- $xmm0 = MOVSDrm killed $rax, 1, $noreg, 0, $noreg :: (load 8 from constant-pool)
+ $xmm0 = MOVSDrm_alt killed $rax, 1, $noreg, 0, $noreg :: (load 8 from constant-pool)
bb.12.bb51:
liveins: $ebp, $rbx, $xmm0
Modified: llvm/trunk/test/CodeGen/X86/pr30821.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30821.mir?rev=363643&r1=363642&r2=363643&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr30821.mir (original)
+++ llvm/trunk/test/CodeGen/X86/pr30821.mir Mon Jun 17 20:23:11 2019
@@ -89,10 +89,10 @@ body: |
%1:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
; First faulty sequence; %1 spilt
- %12:fr64 = MOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
+ %12:fr64 = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
%13:vr128 = COPY killed %12
MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %13 :: (volatile store 16 into %ir.india)
- ; CHECK: renamable $xmm{{[0-9]+}} = MOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
+ ; CHECK: renamable $xmm{{[0-9]+}} = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
; CHECK-NEXT: MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed renamable $xmm{{[0-9]+}} :: (volatile store 16 into %ir.india)
; Store %1 to avoid it being optimised out, will result in a load-from-spill
@@ -102,11 +102,11 @@ body: |
; will get coloured and merged.
%2:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %22:fr64 = MOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
+ %22:fr64 = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
%23:vr128 = COPY killed %22
MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %23 :: (volatile store 16 into %ir.india)
- ; CHECK: renamable $xmm{{[0-9]+}} = MOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
+ ; CHECK: renamable $xmm{{[0-9]+}} = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 8 from %ir.india)
; CHECK-NEXT: MOVAPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed renamable $xmm{{[0-9]+}} :: (volatile store 16 into %ir.india)
MOVUPDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %2 :: (volatile dereferenceable store 16 into %ir.india)
@@ -115,7 +115,7 @@ body: |
; Test some sequences that _should_ be eliminated
%3:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %32:fr64 = VMOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
+ %32:fr64 = VMOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
%33:fr64 = COPY killed %32
VMOVSDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %33 :: (store 8 into %ir.india)
@@ -130,7 +130,7 @@ body: |
; Moves with different encodings but same size should be eliminated
%4:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %42:fr32 = MOVSSrm %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 4 from %ir.india)
+ %42:fr32 = MOVSSrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 4 from %ir.india)
%43:fr32 = COPY killed %42
VMOVSSZmr %stack.2.india, 1, $noreg, 0, $noreg, killed %43 :: (store 4 into %ir.india)
@@ -143,7 +143,7 @@ body: |
; Same deal with double-size
%5:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %52:fr64 = MOVSDrm %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
+ %52:fr64 = MOVSDrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
%53:fr64 = COPY killed %52
VMOVSDZmr %stack.2.india, 1, $noreg, 0, $noreg, killed %53 :: (store 8 into %ir.india)
@@ -156,7 +156,7 @@ body: |
; Last two repeated, with load/store opcode flipped
%6:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %62:fr32 = VMOVSSZrm %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 4 from %ir.india)
+ %62:fr32 = VMOVSSZrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 4 from %ir.india)
%63:fr32 = COPY killed %62
MOVSSmr %stack.2.india, 1, $noreg, 0, $noreg, killed %63 :: (store 4 into %ir.india)
@@ -169,7 +169,7 @@ body: |
; Flipped double-size different-encoding test
%7:vr128 = MOVUPDrm %stack.2.india, 1, $noreg, 0, $noreg :: (volatile dereferenceable load 16 from %ir.india)
- %72:fr64 = VMOVSDZrm %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
+ %72:fr64 = VMOVSDZrm_alt %stack.2.india, 1, $noreg, 0, $noreg :: (dereferenceable load 8 from %ir.india)
%73:fr64 = COPY killed %72
MOVSDmr %stack.2.india, 1, $noreg, 0, $noreg, killed %73 :: (store 8 into %ir.india)
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