[PATCH] D63430: [ARM] Add support for the MVE long shift instructions
Sam Tebbs via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 17 07:36:01 PDT 2019
samtebbs created this revision.
samtebbs added reviewers: samparker, dmgreen, SjoerdMeijer, t.p.northover, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.
The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.
test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.
https://reviews.llvm.org/D63430
Files:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/ARM/shift_parts.ll
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