[PATCH] D63411: [WIP][RISCV] Specify registers used in DWARF exception handling
Edward Jones via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 17 04:42:16 PDT 2019
edward-jones created this revision.
edward-jones added reviewers: asb, lewis-revill.
Herald added subscribers: llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
Herald added a project: LLVM.
Defines RISCV registers for getExceptionPointerRegister() and getExceptionSelectorRegister()
Repository:
rL LLVM
https://reviews.llvm.org/D63411
Files:
lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/RISCV/RISCVISelLowering.h
Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -126,6 +126,16 @@
return true;
}
+ /// If a physical register, this returns the register that receives the
+ /// exception address on entry to an EH pad.
+ unsigned
+ getExceptionPointerRegister(const Constant *PersonalityFn) const override;
+
+ /// If a physical register, this returns the register that receives the
+ /// exception typeid on entry to a landing pad.
+ unsigned
+ getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
+
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2353,3 +2353,13 @@
Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
return Result;
}
+
+unsigned RISCVTargetLowering::getExceptionPointerRegister(
+ const Constant *PersonalityFn) const {
+ return RISCV::X10;
+}
+
+unsigned RISCVTargetLowering::getExceptionSelectorRegister(
+ const Constant *PersonalityFn) const {
+ return RISCV::X11;
+}
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