[PATCH] D63390: [Codegen] TargetLowering::SimplifySetCC(): omit urem when possible
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 16 15:25:03 PDT 2019
lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper.
lebedev.ri added a project: LLVM.
This addresses the regression that is being exposed by D50222 <https://reviews.llvm.org/D50222> in `test/CodeGen/X86/jump_sign.ll`
The missing fold, at least partially, looks trivial:
https://rise4fun.com/Alive/Zsln
i.e. if we are comparing with zero, and comparing the `urem`-by-non-power-of-two,
and the `urem` is of something that may at most have a single bit set (or no bits set at all),
the `urem` is not needed.
Repository:
rL LLVM
https://reviews.llvm.org/D63390
Files:
lib/CodeGen/SelectionDAG/TargetLowering.cpp
test/CodeGen/X86/jump_sign.ll
Index: test/CodeGen/X86/jump_sign.ll
===================================================================
--- test/CodeGen/X86/jump_sign.ll
+++ test/CodeGen/X86/jump_sign.ll
@@ -397,14 +397,11 @@
; CHECK-LABEL: func_test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl b, %eax
-; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: setb %cl
; CHECK-NEXT: movl a, %eax
-; CHECK-NEXT: andl %eax, %ecx
-; CHECK-NEXT: imull $-85, %ecx, %ecx
-; CHECK-NEXT: cmpb $86, %cl
-; CHECK-NEXT: jb .LBB18_2
+; CHECK-NEXT: testb %al, %cl
+; CHECK-NEXT: je .LBB18_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: decl %eax
; CHECK-NEXT: movl %eax, a
Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3025,6 +3025,23 @@
}
}
+ // Given:
+ // icmp eq/ne (urem %x, C), 0
+ // Iff C is not a power of two (those should not get to here though),
+ // and %x may have at most one bit set, omit the 'urem':
+ // icmp eq/ne %x, 0
+ if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+ if (auto *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1).getNode())) {
+ // We shouldn't have 'urem %x, power-of-2' by now, but just to be sure.
+ if (!N01C->getAPIntValue().isPowerOf2()) {
+ KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
+ if (Known.countMaxPopulation() == 1)
+ return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
+ }
+ }
+ }
+
if (SDValue V =
optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
return V;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63390.204968.patch
Type: text/x-patch
Size: 1855 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190616/1e16bbef/attachment.bin>
More information about the llvm-commits
mailing list