[PATCH] D63351: [AMDGPU] gfx10 conditional registers handling

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL363513: [AMDGPU] gfx10 conditional registers handling (authored by rampitec, committed by ).
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D63351?vs=204824&id=204957#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63351/new/

https://reviews.llvm.org/D63351

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
  llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
  llvm/trunk/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir

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