[llvm] r363517 - AMDGPU: Prepare for explicit absolute relocations in code generation
Nicolai Haehnle via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 16 10:43:38 PDT 2019
Author: nha
Date: Sun Jun 16 10:43:37 2019
New Revision: 363517
URL: http://llvm.org/viewvc/llvm-project?rev=363517&view=rev
Log:
AMDGPU: Prepare for explicit absolute relocations in code generation
Summary:
We will use absolute relocations for LDS symbols.
Change-Id: I9a32795ed0ea835e433a787129cfe3c57ee9a325
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61492
Modified:
llvm/trunk/include/llvm/MC/MCExpr.h
llvm/trunk/lib/MC/MCExpr.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir
Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Sun Jun 16 10:43:37 2019
@@ -293,6 +293,8 @@ public:
VK_AMDGPU_REL32_LO, // symbol at rel32@lo
VK_AMDGPU_REL32_HI, // symbol at rel32@hi
VK_AMDGPU_REL64, // symbol at rel64
+ VK_AMDGPU_ABS32_LO, // symbol at abs32@lo
+ VK_AMDGPU_ABS32_HI, // symbol at abs32@hi
VK_TPREL,
VK_DTPREL
Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Sun Jun 16 10:43:37 2019
@@ -310,6 +310,8 @@ StringRef MCSymbolRefExpr::getVariantKin
case VK_AMDGPU_REL32_LO: return "rel32 at lo";
case VK_AMDGPU_REL32_HI: return "rel32 at hi";
case VK_AMDGPU_REL64: return "rel64";
+ case VK_AMDGPU_ABS32_LO: return "abs32 at lo";
+ case VK_AMDGPU_ABS32_HI: return "abs32 at hi";
}
llvm_unreachable("Invalid variant kind");
}
@@ -425,6 +427,8 @@ MCSymbolRefExpr::getVariantKindForName(S
.Case("rel32 at lo", VK_AMDGPU_REL32_LO)
.Case("rel32 at hi", VK_AMDGPU_REL32_HI)
.Case("rel64", VK_AMDGPU_REL64)
+ .Case("abs32 at lo", VK_AMDGPU_ABS32_LO)
+ .Case("abs32 at hi", VK_AMDGPU_ABS32_HI)
.Default(VK_Invalid);
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp Sun Jun 16 10:43:37 2019
@@ -90,6 +90,10 @@ static MCSymbolRefExpr::VariantKind getV
return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
case SIInstrInfo::MO_REL32_HI:
return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
+ case SIInstrInfo::MO_ABS32_LO:
+ return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
+ case SIInstrInfo::MO_ABS32_HI:
+ return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
}
}
@@ -146,10 +150,13 @@ bool AMDGPUMCInstLower::lowerOperand(con
SmallString<128> SymbolName;
AP.getNameWithPrefix(SymbolName, GV);
MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
- const MCExpr *SymExpr =
+ const MCExpr *Expr =
MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
- const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
- MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
+ int64_t Offset = MO.getOffset();
+ if (Offset != 0) {
+ Expr = MCBinaryExpr::createAdd(Expr,
+ MCConstantExpr::create(Offset, Ctx), Ctx);
+ }
MCOp = MCOperand::createExpr(Expr);
return true;
}
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp Sun Jun 16 10:43:37 2019
@@ -399,8 +399,12 @@ SIMCCodeEmitter::getSDWAVopcDstEncoding(
static bool needsPCRel(const MCExpr *Expr) {
switch (Expr->getKind()) {
- case MCExpr::SymbolRef:
- return true;
+ case MCExpr::SymbolRef: {
+ auto *SE = cast<MCSymbolRefExpr>(Expr);
+ MCSymbolRefExpr::VariantKind Kind = SE->getKind();
+ return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO &&
+ Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
+ }
case MCExpr::Binary: {
auto *BE = cast<MCBinaryExpr>(Expr);
if (BE->getOpcode() == MCBinaryExpr::Sub)
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Sun Jun 16 10:43:37 2019
@@ -5846,7 +5846,9 @@ SIInstrInfo::getSerializableDirectMachin
{ MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" },
{ MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" },
{ MO_REL32_LO, "amdgpu-rel32-lo" },
- { MO_REL32_HI, "amdgpu-rel32-hi" }
+ { MO_REL32_HI, "amdgpu-rel32-hi" },
+ { MO_ABS32_LO, "amdgpu-abs32-lo" },
+ { MO_ABS32_HI, "amdgpu-abs32-hi" },
};
return makeArrayRef(TargetFlags);
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Sun Jun 16 10:43:37 2019
@@ -143,7 +143,7 @@ protected:
public:
enum TargetOperandFlags {
- MO_MASK = 0x7,
+ MO_MASK = 0xf,
MO_NONE = 0,
// MO_GOTPCREL -> symbol at GOTPCREL -> R_AMDGPU_GOTPCREL.
@@ -160,7 +160,10 @@ public:
MO_REL32_HI = 5,
MO_LONG_BRANCH_FORWARD = 6,
- MO_LONG_BRANCH_BACKWARD = 7
+ MO_LONG_BRANCH_BACKWARD = 7,
+
+ MO_ABS32_LO = 8,
+ MO_ABS32_HI = 9,
};
explicit SIInstrInfo(const GCNSubtarget &ST);
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir?rev=363517&r1=363516&r2=363517&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir Sun Jun 16 10:43:37 2019
@@ -26,7 +26,9 @@ body: |
; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
; CHECK: S_ENDPGM 0
%0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
- %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+ %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+ %2:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @foo
+ %3:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @foo
S_ENDPGM 0
...
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